1. Lecture 3 ALU and Carry Generator using FPGA 2007/09/21 Prof. C.M. Kyung

2. 2/13 ALU and Carry Generator using FPGA 1. Experimental GOAL is (1) Learning how to design one of the most important subsystems in a digital computer: the arithmetic logic unit or ALU (2) Understanding and design basic circuits such as RCA (Ripple Carry Adder) and CLA (Carry Look-ahead Adder) (3) Manipulating binary numbers

3. 3/13 ALU and Carry Generator using FPGA 2. Adder & ALU (1) Full Adder (2) n-bit RCA (Ripple Carry Adder) (3) CLA (Carry Look-ahead Adder)

4. 4/13 ALU and Carry Generator using FPGA 2. Adder & ALU (2) n-bit RCA (Ripple Carry Adder) - Series of full adder - Carry bit ripples from one bit to the next bit - Simple, but slow since each FA must wait for the carry bit to be calculated from the previous FA c0c0 cncn c1c1 c2c2 c n-1

5. 5/13 ALU and Carry Generator using FPGA (3) CLA (Carry Look-ahead Adder) - Express each Ci in terms of A i, A i-1, …, A 0, B i, B i-1, …, B 0 and C 0 directly - Complicated, but fast - P i : Whether a i-th carry out is propagated through from i-th carry in - G i : A carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0

6. 6/13 ALU and Carry Generator using FPGA (3) CLA (Carry Look-ahead Adder) - Sum of i-th stage - Carry out of i-th stage

7. 7/13 ALU and Carry Generator using FPGA (3) CLA (Carry Look-ahead Adder) - Block diagram of 16-bit CLA

8. 8/13 ALU and Carry Generator using FPGA (4) ALU (Arithmetic Logic Unit) - General purpose device capable of various arithmetic and logical operations - The “heart” of a processor

9. 9/13 ALU and Carry Generator using FPGA 3. Problem statement (1) Full Adder (2) n-bit RCA (Ripple Carry Adder) (3) CLA (Carry Look-ahead Adder) (4) Arithmetic Logic Unit

10. 10/13 ALU and Carry Generator using FPGA 4. Experiment Requirements (1) Quartus II - Read supplement & follow directions (2) Verilog - Hardware Description Language - Example: synchronous 3-bit ring up-counter

11. 11/13 ALU and Carry Generator using FPGA 4. Experiment Requirements (2) Verilog - Example: synchronous 3-bit ring up-counter

12. 12/13 ALU and Carry Generator using FPGA 4. Experiment Requirements (2) Verilog - Example: synchronous 3-bit ring up-counter

13. 13/13 ALU and Carry Generator using FPGA 5. References (1) Textbook - Contemporary Logic Design- Katz - Fundamentals of Logic Design- Roth (2) 3 rd Week T.A. E-mail jsjeong@dtlab.kaist.ac.kr ejchoi@dtlab.kaist.ac.kr (3) Lecture Homepage http://wink.kaist.ac.kr/course/ee306/