1. Revisão de Circuitos Lógicos PARTE III

2. Review Use this table and techniques we learned to transform from 1 to another

3. Today Common Combinational Logic Blocks Data Multiplexors Arithmetic and Logic Unit Adder/Subtractor

4. Data Multiplexor (here 2-to-1, n-bit-wide) “mux”

5. N instances of 1-bit-wide mux How many rows in TT?

6. How do we build a 1-bit-wide mux?

7. 4-to-1 Multiplexor? How many rows in TT?

8. Is there any other way to do it? Hint: March Madness Ans: Hierarchically!

9. C P Q 0 1 D DC 0P 1Q Do you really understand NORs? If one input is 1, what is a NOR ? If one input is 0, what is a NOR ? A B NOR 0 0 1 0 1 0 1 0 0 1 1 0 A B NO R A 0B’ 10 A _B_B 0 NOR

10. C P Q 0 1 D DC 0P 1Q Do you really understand NANDs? If one input is 1, what is a NAND ? If one input is 0, what is a NAND ? A B NAND 0 0 1 0 1 1 1 0 1 1 1 0 A NAN D 01 1B’ A 1 _B_B NAND A B

11. Arithmetic and Logic Unit Most processors contain a special logic block called “Arithmetic and Logic Unit” (ALU) We’ll show you an easy one that does ADD, SUB, bitwise AND, bitwise OR

12. Our simple ALU

13. Adder/Subtracter Design -- how? Truth-table, then determine canonical form, then minimize and implement as we’ve seen before Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer

14. Adder/Subtracter – One-bit adder LSB…

15. Adder/Subtracter – One-bit adder (1/2)…

16. Adder/Subtracter – One-bit adder (2/2)…

17. N 1-bit adders  1 N-bit adder What about overflow? Overflow = c n ? +++ b0b0

18. What about overflow? Consider a 2-bit signed # & overflow: 10 = -2 + -2 or -1 11 = -1 + -2 only 00 = 0 NOTHING! 01 = 1 + 1 only Highest adder C 1 = Carry-in = C in, C 2 = Carry-out = C out No C out or C in  NO overflow! C in, and C out  NO overflow! C in, but no C out  A,B both > 0, overflow! C out, but no C in  A,B both < 0, overflow! ± # What op?

19. What about overflow? Consider a 2-bit signed # & overflow: 10 = -2 + -2 or -1 11 = -1 + -2 only 00 = 0 NOTHING! 01 = 1 + 1 only Overflows when… C in, but no C out  A,B both > 0, overflow! C out, but no C in  A,B both < 0, overflow! ± #

20. Extremely Clever Subtractor

21. Taking advantage of sum-of-products Since sum-of-products is a convenient notation and way to think about design, offer hardware building blocks that match that notation One example is Programmable Logic Arrays (PLAs) Designed so that can select (program) ands, ors, complements after you get the chip Late in design process, fix errors, figure out what to do later, …

22. inputs AND array outputs OR array product terms Programmable Logic Arrays Pre-fabricated building block of many AND/OR gates “Programmed” or “Personalized" by making or breaking connections among gates Programmable array block diagram for sum of products form And Programming: How many inputs? How to combine inputs? How many product terms? Or Programming: How to combine product terms? How many outputs?

23. example: F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A personality matrix 1 = uncomplemented in term 0 = complemented in term – = does not participate 1 = term connected to output 0 = no connection to output input side: 3 inputs output side: 4 outputs Product inputsoutputs termABCF0F1F2F3 AB11–0110 B'C–010001 AC'1–00100 B'C'–001010 A1––1001 reuse of terms; 5 product terms Enabling Concept Shared product terms among outputs

24. Before Programming All possible connections available before “programming”

25. After Programming Unwanted connections are "blown" Fuse (normally connected, break unwanted ones) Anti-fuse (normally disconnected, make wanted connections)

26. notation for implementing F0 = A B + A' B' F1 = C D' + C' D AB+A'B' CD'+C'D AB A'B' CD' C'D ABCD Alternate Representation Short-hand notation--don't have to draw all the wires X Signifies a connection is present and perpendicular signal is an input to gate

27. Peer Instruction A. Truth table for mux with 4-bits of select signal has 2 4 rows B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl C. If 1-bit adder delay is T, the N-bit adder delay would also be T ABC 0: FFF 1: FFT 2: FTF 3: FTT 4: TFF 5: TFT 6: TTF 7: TTT

28. Peer Instruction Answer A. Truth table for mux with 4-bits of signals is 2 4 rows long B. We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl C. If 1-bit adder delay is T, the N-bit adder delay would also be T ABC 0: FFF 1: FFT 2: FTF 3: FTT 4: TFF 5: TFT 6: TTF 7: TTT A.Truth table for mux with 4-bits of signals controls 16 inputs, for a total of 20 inputs, so truth table is 2 20 rows…FALSE B.We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl … TRUE C.What about the cascading carry? FALSE

29. Combinational Logic from 10 miles up CL circuits simply compute a binary function (e.g., from truthtable) Once the inputs go away, the outputs go away, nothing is saved, no STATE Similar to a function in Scheme with no set! or define to save anything How does the computer remember data? [e.g., for registers] X Y X Y Z (define (xor x y) (or (and (not x) y) (and x (not y))))

30. State Circuits Overview State circuits have feedback, e.g. Output is function of inputs + fed-back signals. Feedback signals are the circuit's state. What aspects of this circuit might cause complications? Combi-national Logic

31. A simpler state circuit: two inverters When started up, it's internally stable. Provide an or gate for coordination: What's the result? 010 010 0 0 0 1! 1 10 1 1 How do we set to 0?

32. 0 Hold! An R-S latch (cross-coupled NOR gates) S means “set” (to 1), R means “reset” (to 0). Adding Q’ gives standard RS-latch: Truth table S R Q 0 0 hold (keep value) 0 1 0 1 0 1 1 1 unstable A B NOR 0 0 1 0 1 0 1 0 0 1 1 0 _Q_Q 0 1 0 0 0 1 1 0 1 1 1 0 0 0 1 0 01 0 1 Hold! 0

33. An R-S latch (in detail) Truth table _ S R Q Q Q(t+  t) 0 0 0 1 0 hold 0 0 1 0 1 hold 0 1 0 1 0 reset 0 1 1 0 0 reset 1 0 0 1 1 set 1 0 1 0 1 set 1 1 0 x x unstable 1 1 1 x x unstable A B NOR 0 0 1 0 1 0 1 0 0 1 1 0

34. Controlling R-S latch with a clock Can't change R and S while clock is active. Clocked latches are called flip-flops. A B NOR 0 0 1 0 1 0 1 0 0 1 1 0

35. D flip-flop are what we really use Inputs C (clock) and D. When C is 1, latch open, output = D (even if it changes, “transparent latch”) When C is 0, latch closed, output = stored value. C D AND 0 0 0 0 1 0 1 0 0 1 1 1

36. D flip-flop details We don’t like transparent latches We can build them so that the latch is only open for an instant, on the rising edge of a clock (as it goes from 0  1) D C Q Timing Diagram

37. “And In conclusion…” Use muxes to select among input S input bits selects 2 S inputs Each input can be n-bits wide, indep of S Can implement muxes hierarchically ALU can be implemented using a mux Coupled with basic block elements N-bit adder-subtractor done using N 1-bit adders with XOR gates on input XOR serves as conditional inverter Latches are used to implement flip-flops