1. HALL A Moller Polarimeter Requirement 1 2 3 4 SCIN TILL ATOR 1 2 3 4 CAL ORI MET ER LEFT 1 2 3 4 SCIN TILL ATOR 1 2 3 4 CAL ORI MET ER RIGHT FADC-250 4 4 4 4 ON BOARD SCALER (COUNTER) to be read out by a separate trigger (helicity and gate bits) at the helicity cycle of 30 to 2kHz. CL and CR CL and SL CR and SR CL and CR and SL and SR CL and CR and (SL and SR delayed > 100 ns) TRIGGER condition (or): CL.AND.CR prescaled from 1 to at least 1000 CL prescaled from 1 to at least 1000 CR prescaled from 1 to at least 1000 CL = Σ I=1,4 ∑ j=1,2 P J I > threshold CR = Σ I=1,4 ∑ j=1,2 P J I > threshold SL = (Σ J=1,2 S1 J > threshold) or (ΣJ=1,2 S2 J > threshold) or (ΣJ=1,2 S3 J > threshold) or (ΣJ=1,2 S4 J > threshold) SR = (Σ J=1,2 S5 J > threshold) or (ΣJ=1,2 S6 J > threshold) or (ΣJ=1,2 S7 J > threshold) or (ΣJ=1,2 S8 J > threshold) When TRIGGER condition is met, send data that cause TRIGGER. 1-4 5-8 9-1213-16

2. Xilinx LX25 ADC 16 9 ADC 8 1 Xilinx LX25 Xilinx FX20 24 FIFO ALTERA STRATIX2 Control Bus Front Panel Lvds Trig, Sync BACK Plane Trig, Sync VME BUS 3 2 2 FADC HARDWARE ARCHITECTURE

3. Xilinx LX25 ADC L Calorimeter ( ADC 16..13) ADC Xilinx LX25 Xilinx FX20 Cal Sum 16) Scint Hit (4) FIFO ALTERA STRATIX2 Trig Type, Trig Count, Helicity, Gate Front Panel Helicity Gate VME BUS trigger MOLLER DAQ FIRMWARE ARCHITECTURE TOP LEVEL trigger Trig Ready Capture Data Cal Sum 16) Scint Hit (4) R Calorimeter (ADC 8..5) L Scint (ADC12..9) R Scint (ADC 4..1)

4. MOLLER DAQ FIRMWARE ARCHITECTURE Xilinx LX25 TRIGGER Cal 1 0 G en1 Cal 4 0 G en4 Scint1 0 G en5 Scint4 0 G en8 No change to Look Back Algorithm 8 0 S en1 0 GS en4 + SUM G  Global REG + + > Threshold > HIT Threshold SL = ∑ j=1,2 S J > Th x SR = ∑ j=1,2 S J > Th x C = Σ I=1,4 P I HISTORY Cal 1-4 Scint 1-4 Trigger Capture Data To FIFO /2

5. Trigger to ALtera FPGA Hit Pattern to FIFO enable Trig Ready from ALtera FPGA MOLLER DAQ FIRMWARE ARCHITECTURE Xilinx FX20 1 st LX25 SUM CR 2 nd LX25 SUM CL 1 st LX 25 HIT Px DELAY 2 nd LX 25 HIT Px DELAY 4 4 TRIGGER LOGIC En Clear 32 bits Counter En Clear 32 bits Counter En Clear 32 bits Counter En Clear 32 bits Counter CONTROLBUSCONTROLBUS AUX(0) AUX(1) CNT_CTRL bit from Altera TRIG TYPE (CR*CL) (CL*SL) (CR*SR) (CL*CR*SL*SR) CL CR P Prescalar Trig pattern Trig Type P  Programmable SR SL 4 4 Px DELAY -2X-Pn1 + - + > Px FixWidth P Threshold Px DELAY -2X-Pn1 + - + > P Threshold Px FixWidth SL SR Px DELAY (min 100 ns) d(SL*SR) En Clear 32 bits Counter (CL*CR*d(SL*SR) Helicity(aux2), TrigCount CL = ∑ j=1,2 P J CR = ∑ j=1,2 P J En 12 bits Counter Trig Ready Hit Window

6. CL_Prescale CR_Prescale CLandCR Prescale CL CR CLandCR Trigger MOLLER DAQ FIRMWARE ARCHITECTURE Xilinx FX20 (Hit Window) Clr En Counter = 8 s c c e c e c e

7. MOLLER DAQ FIRMWARE ARCHITECTURE Altera FPGA Control FRONT PANEL HELICITY TRIG FROM FX20 TRIG READY TO FX20 AUX(0)TO FX20 TRIG TO LX25