2. 1 VLSI Design Lecture Four Design & Testing Issues Dr. Richard Spillman PLU Spring 2003

3. PLU Spr 02 2 Semester Topics Introduction MOS/CMOS FPGAsPhysical Design

4. PLU Spr 02 3 Review  IC Fab  Design Rules  Pass Transistors  CMOS Technology

5. PLU Spr 02 4 nMOSpMOS Review – CMOS NAND V dd b b a ab gnd a b ab 0 0 1 1 0 1 1 1 1 0

6. PLU Spr 02 5 Outline  AOI Design  AOI Layout  AOI for nMOS  Testing

7. PLU Spr 02 6 CMOS Circuit Design  Given a complex CMOS circuit, there are two major design approaches  Design the circuit using logic gates and implement each gate in CMOS  cost: 4 transistors per gate (at least)  generates a lot of wires  Design the circuit using logic gates and implement a CMOS version of AOI  AND/OR/INVERT  uses series & parallel MOSFETS

8. PLU Spr 02 7 Method One  GOAL: Design a circuit which will implement: F = AB + CD PROCESS PROCESS: Design the logic circuit and implement each gate in CMOS COST: 6 transistors for each AND (4 for the NAND and 2 for the inverter) or 16 transistors

9. PLU Spr 02 8 Method Two  AOI Approach - form a compound circuit as a combination of series and parallel MOSFET’s (AND’s in series, OR’s in parallel)  STEP ONE: Design the n-side circuit using n-type MOS devices  form the AND terms, in this case AB and CD F = AB + CD A B C D

10. PLU Spr 02 9 Method Two (continued)  STEP TWO - form the OR as a parallel connection A B C D

11. PLU Spr 02 10 Method Two (continued)  STEP THREE - Design the p-side circuit using p-type MOS devices  complement the n-side circuit (AB + CD) = (A + B)(C + D)

12. PLU Spr 02 11 Method Two (continued)  STEP FOUR - form the OR terms of this expression A B C D (A + B)(C + D) AND’s in series, OR’s in parallel)

13. PLU Spr 02 12 Method Two (continued)  STEP FIVE - form the AND A B C D (A + B)(C + D) AND’s in series, OR’s in parallel)

14. PLU Spr 02 13 Method Two (continued)  STEP SIX: put the n-side and the p-side together A B C D A B C D F COST: 8 transistors or a 50% savings

15. PLU Spr 02 14 General Method  This design approach may be implemented using K-Maps  for the n-side design, loop the 0’s  for the p-side design, loop the 1’s  RULE: OR’s in parallel, AND’s in series  EXAMPLE  Design the circuit for F=(A+B+C)D

16. PLU Spr 02 15Circuit A B D C 0001 11 10 00 01 11 10 1 1 1 1 1 1 1 1 1 D +ABC A B D C 0001 11 10 00 01 11 10 0 0 0 0 0 0 0 (A+B+C)D A B C D D ABC F

17. PLU Spr 02 16 AOI Layout  Given an AOI CMOS version of F = (a+b)c  the layout depends on the order of the inputs a a b c +V gnd c b Change the order of the inputs PROBLEM: How do we determine the best order?

18. PLU Spr 02 17 Net Graphs Nodes are connection points, links are transistors

19. PLU Spr 02 18 Complete Graph

20. PLU Spr 02 19 Input Order  Note the breaks in the diffusion path

21. PLU Spr 02 20 Example Find an Euler path which is common to the p and n graphs

22. PLU Spr 02 21 AOI for nMOS  As with CMOS, each AND device can be viewed as a series connection and each OR device can be viewed as a parallel connection  However, an nMOS circuit requires a pull-up transistor  AOI design uses a single pull-up for the entire circuit

23. PLU Spr 02 22 Example One G=(E+F)A + BC A F E B C G pull up +V gnd RULE: Parallel for OR Series for AND

24. PLU Spr 02 23 Example Two G = A B For an AOI implementation, however, the output must be asserted low, so G must be restructured as: G = AB + AB = A B X

25. PLU Spr 02 24Implementation Note the inverters are not part of the AOI A B G +V gnd

26. PLU Spr 02 25 Introduction to Testing  PROBLEM: Determine, in a cost effective way, whether a component, module, chip, or board has been manufactured correctly  A fault is a condition in a circuit that will yield incorrect results for a given input pattern  Our fault model will be the stuck-at model which assumes that a logic gate input or output is fixed at logic 1 or logic 0  The percentage of single stuck-at faults that a given test sequence will detect is called the fault coverage

27. PLU Spr 02 26 Testing Areas  Two problem areas  Test Generation  because of the size of VLSI circuits, automatic test generators are required yet for combinational circuits fault coverage begins to drop after 5000 gates and for sequential circuits it begins to drop after 1000 gates  hence, ATPG are supplemented with manually generated tests which is expensive and time consuming  Fault Simulation  Fault simulation must be used to determine fault coverage yet this is also expensive

28. PLU Spr 02 27 Testing Cost  An estimate of the time to generate and simulate a test set for a circuit with N gates is: T = kN 3 RESULT: it is hard to test VLSI chips

29. PLU Spr 02 28 Defect Level Impact  Consider the relationship between the defect level on a chip, the level of fault coverage for a test set, and the yield of a chip production process  Assume that faults are uniformly distributed and independent, the tests applied have a fault coverage of T (0 < T < 1) and the production process has a yield of Y (0 < Y < 1)  The defect level, DL (after testing) is DL = 1 - Y (1-T)

30. PLU Spr 02 29 Example  If a chip manufacturing process has a yield of.15 (15% of the chips are good) then without testing (T = 0) the defect level is DL = 1 - (.15) 1 =.85 85% of the chips produced and shipped are bad if a test set with a fault cover of 75% is applied, then DL = 1 - (.15).25 =.40 40% of the chips shipped would be bad

31. PLU Spr 02 30 Requirement  Since testing can represent as much as 50% of a product cost, it is important to develop two approaches:  Efficient test set construction: quick and inexpensive algorithms for testing a new circuit  Design for test procedures: design procedures which make test set construction easy for circuits that are complex

32. PLU Spr 02 31 Fault Model  Before a testing procedure can be developed, it is necessary to define a fault a b c the most common model is the stuck-at model almost all failures in a logic gate appear as an input or output line stuck at 0 or stuck at 1 the result is that when the fault exists, some inputs may actually produce the correct output while others will produce the wrong output a s-a-1 a b f-f 0 0 1 1 0 1 00010001 a s-a-1 0 1 0 1 Test WHY?

33. PLU Spr 02 32 Path Sensitization  GOAL: Develop a test generation method based on the topological gate level description of the circuit  Conditions for fault detection  Necessary Condition: to detect the fault, line h s-a-j, the inputs must be selected so that line h takes on the value (not j) in the fault free circuit  Sufficient Condition: to detect the fault on line h, the inputs must be selected so that the output value depends on the value of line h

34. PLU Spr 02 33Example NECESSARY: ? SUFFICIENT: Select the other inputs so that Z depends on x 3 NECESSARY: x 3 = 0 s-a-1 ?1

35. PLU Spr 02 34Algorithm  Select the inputs so as to generate the appropriate value (0 for s-a-1 or 1 for s-a-0) at the site of the fault  Select a path from the site of the fault to an output and specify additional signal values to propagate the fault along this path (error propagation)  Specify input values so as to produce the signal values specified above (line justification)

36. PLU Spr 02 35Example h s-a-1 Test for h s-a-1 0 on h (1 if faulty) 0/1 Propagate to 3 0/1? 1 Propagate to f 0/1? 0 Justify line 1??0 0 0 Justify line 4 ??0 Test Input x 1 x 2 x 3 x 4 1 2 3 4 f

37. PLU Spr 02 36 Testable Design  NEED: A method to design chips so that they are easy to test and for which it is easy to develop test sets with high fault coverage Two key concepts Controllability: the ease with which a network can be “steered” through its various functions Observability: the ease with which internal states of the network can be examined Design for Testability, DFT

38. PLU Spr 02 37 Ad Hoc Design  This is the first of two general approaches to DFT  It is the use of inexpensive methods which apply to specific circuits but which may not apply in general to all circuits  ranges from suggested guidelines to detailed circuit analysis techniques  Guidelines: Avoid logically redundant circuits, isolates clocks from logic...

39. PLU Spr 02 38 Partitioning  There are two reasons for partitioning a circuit for testing purposes  the circuit is to large for the test generation tools  the circuit has to many inputs for exhaustive testing  A small combinational logic circuit with n inputs can be tested by trying all 2n input combinations. However, if the circuit has 64 inputs with one of the 264 input combinations applied every nsec, it would take 585 years to complete the test. Partitioning the circuit into two blocks of 32 inputs each would reduce the testing time to 9 seconds.

40. PLU Spr 02 39 Degating  One approach to partitioning involves degating  adding extra gates to allow modules to be isolated during the testing process Logic Block A Logic Block B Test Out If Test = 0 then only Logic Block A affects the output

41. PLU Spr 02 40 Test Points  Test points are control points (inputs) or observation points (outputs) added to a circuit to reduce the number of tests required for fault detection  Candidate sites for control and observation points are:  the outputs of flip/flops  the set or reset input of flip/flops  the junctions of large fan-in or fan-outs  data or address bus lines  master clock lines

42. PLU Spr 02 41 Example C1C2 Difficult to control and observe Add a MUX Test Mode CP OP 0101

43. PLU Spr 02 42 Structured Design  This is the second major approach to DFT  It involves the use of uniform design methods for latches  Possible methods include:  Level-Sensitive Scan Design, LSSD  Random-Access Scan  Scan Path  Scan/Set Logic

44. PLU Spr 02 43 Level Sensitive Scan Design  LSSD is the most widely used method for testable design  it was developed by IBM in 1978  LSSD imposes a clocked structure on all memory elements and forms the elements into shift register latches, making it possible to shift values into and out of the elements by way of a scan path

45. PLU Spr 02 44 LSSD Model  LSSD structure is based on the separation of combinational logic and memory Combinational Circuit Memory Add components so memory behaves like a shift register

46. PLU Spr 02 45 Shift Register Latch  Acts like a DFF or a Shift Register element D clk I ShiftA L1 L2 L1 ShiftB L2 NORMAL OPERATION: ShiftA and ShiftB are off and the device operates like a DFF on L1 SHIFT OPERATION: I is shifted into L1 by Shift A L1 is loaded into L2 by ShiftB

47. PLU Spr 02 46 Shift Register String  A shift register string is formed by connecting the L2 output of one SRL to the I input of the next and by connecting all the Shift A and Shift B clock inputs in parallel D1 clk I ShiftA ShiftB L1 L2 L1 L2 L3 Scan Out clk D2 1 X X X X 1 1 X X X X 0 1 1 X X XX 1 1 0 0 1 0 1 1 X XXX 0 1 0 1 1XXX 1 0 0 1 1 0 1 0 0 1 0 01XXX 1 1 0 1 1 0

48. PLU Spr 02 47 Testing Application  Under normal operating conditions the system performs its designed function  Under testing conditions, the LSSD structure can be used to observe an unknown state by:  clock B to move the unknown state to L2  then in sequence, clock A - clock B and monitor the scan out signal  The machine can be initialized to a known state by:  input the desired state serially on the Scan-In input  clock A - clock B in sequence until the F/F’s are all set  run the machine in the normal operating mode

49. PLU Spr 02 48 Boundary Scan  Boundary Scan is a process to check for shorts or opens between IC chips on a PCB  It also can find shorts and opens inside a chip

50. PLU Spr 02 49 Boundary Scan Design  Place a scan chain alone the pins of an IC chip: Scan Data In Scan Data Out

51. PLU Spr 02 50 BSD on PCB  Several chips on a PCB can form a large register scan: Normal Mode: BSD inactive Internal Mode: BSD checks the function of a chip External Mode: BSD checks the connections between chips

52. PLU Spr 02 51 Boundary Scan Standard  Since a PCB may contain chips from several manufacturers, there is an IEEE standard for chips with BSD  IEEE standard 1149.1  By following this standard in each chip, any circuit can fit into a BSD test mode

53. PLU Spr 02 52 Chip Standard  IEEE 1149.1 calls for several additional circuits on every chip:

54. PLU Spr 02 53 BSD Control  The control unit consist of a minimum of 4 pins, 3 registers, a mux and associated control logic: TAP: Test Access Port

55. PLU Spr 02 54 Testing Chip Connections  To test the connections between pins: Scan the test pattern into A’s BSD flip/flops A B Send the BSD data alone the pin connections Scan the test results out

56. PLU Spr 02 55 Bypass Mode  Used to skip over chips which are not under test:

57. PLU Spr 02 56 Possible Quiz  Questions that might appear on a quiz include:  What does AOI mean?  Why is testing difficult?  What is the purpose of boundary scan?

58. PLU Spr 02 57 Summary  AOI Design  AOI Layout  AOI for nMOS  Testing It wasn’t so bad