1. 1 Introduction to Engineering Spring 2007 Lecture 19: Digital Tools 3

2. 2 Review Introduction to VHDL Using Xilinx Software

3. 3 Review - VHDL Structure Package Entity Structural Architecture Data Flow Architecture Behavioral Architecture GenericsPortProcess

4. 4 Outline VHDL Statements VHDL Functions Examples

5. 5 VHDL Functions

6. 6 VHDL Statements The body of a process block could contain any of the data flow/behavioral constructs case statement signal assignment statement In addition, it could use other features which are common in HLL: if then else loop structure

7. 7 IF-THEN-ELSE The standard format: if boolean-expression then else end if;

8. 8 Example Consider a comparator circuit It accepts two inputs A and B It produces a “1” output on C if A = B architecture behave of compare is begin process (A,B); begin if (A = B) then C <= ‘1’; else C <= ‘0’; end if; end process; end behave;

9. 9 Loops in VHDL There are 3 types of loops in VHDL for in loop end loop; while loop end loop; loop end loop;

10. 10 Exit Statement exit An exit statement is used to end a loop FORMAT: exit; exit when ; exit ; exit when ;

11. 11 VHDL Functions

12. 12 Functions Functions are used as a short-cut when specifying behavior - therefore, all statements in a function are executed sequentially function A_O_I (constant A1, B1, C1, D1 : in BIT) return BIT is variable the_result : BIT; begin -- any number of sequential statements needed to produce result the_result := (A1 and B1) nor (C1 and D1); return (the_result); end A_O_I; Z <= A_O_I ( A, B,C, D) after 10 ns;

13. 13 General Form The general form of a function is: function func_name ( parameters) return return_type is -- declarations, variables begin -- sequential statements return return_value; end func_name;

14. 14 Example Write a function to convert a bit-vector to a positive integer value. i.e. Binary to Decimal conversion To do this requires three VHDL attributes: Given a variable BV of type BIT_VECTOR( 2 downto 0) BV ’ RANGE is the range of valid indices (2 downto 0) BIT ’ POS (’0’) returns the integer 0 BIT ’ POS (’1’) returns the integer 1

15. 15 Complete Function The conversion function is: function BV_to_NATURAL (BV: in BIT_VECTOR) return INTEGER is variable RESULT : INTEGER := 0; begin for INDEX in BV’RANGE loop result := result * 2 + BIT’POS (BV(INDEX)); end loop; return RESULT; end function BV_to_NATURAL; if BV = "10110", then the integer rep = 2 4 * 1 + 2 3 * 0 + 2 2 * 1 + 2 1 * 1 + 2 0 * 0 = 2 * (2 * ( 2 * ( 2 * ( 1) + 0 ) + 1 ) + 1) + 0

16. 16 Other VHDL Features VHDL is a rich programming language we have covered only the surface some features will be introduced later as they become relevant a few features will be highlighted now VHDL Features attributes generic assignments

17. 17 Attributes An attribute is also a specific property of a signal For example, given a signal S the following attributes can be defined:

18. 18 VHDL Generics Generics allow models to be parameterized that is, general models can be constructed and values passed into them when they are called Generics are defined in the entity: Default value

19. 19 Examples

20. 20 Examples Several examples of VHDL code Multiplexer Decoder Register Adder Clock Signals

21. 21 Multiplexer (MUX) A multiplexer is a digital circuit with several inputs and one output it is designed to pass one selected input on to the output 1 001 Signal set - only one is passed on Used to determine “switch position” Sample data on input Address input 0 Address input 1 Address input 2 Address input 3 Data Address Output 0 1 2 3 0 0 11 02 13

22. 22 MUX Application A MUX is designed to be used as a “data router” for example, a single computer with multiple terminals Computer Mux address data

23. 23 MUX in VHDL A MUX could be described using VHDL in several ways (same entity, different architectures) EXAMPLE: 4-to-1 Mux library ieee; use ieee.std_logic_1164.all; entity MUX4_1 is port (Sel:in std_logic_vector(1 downto 0); A,B,C,D: in std_logic; Y: out std_logic); end MUX4_1; MUX A B C B Sel Y architecture Cond_Data of MUX4_1 is begin Y <= A when Sel = “00” else B when Sel = “01” else C when Sel = “10” else D; end Cond_Data;

24. 24 Decoder A decoder is another digital device which is useful in computer design 0 1 2 3 +v it has n inputs and 2 n outputs one and only one output is asserted for each input combination 0 0 0 0 01 01 1 0 0 0 000 0 1 1 1 1 100 0

25. 25 Decoder Function A decoder will change a binary input into a single asserted output data routing combinational logic design EXAMPLE: four terminals all connected to one computer - the computer wants to send a message to only one terminal Computer T1T1 Decoder T2T2 T3T3 T4T4 address

26. 26 Decoder in VHDL library ieee; use ieee.std_logic_1164.all; entity decode is port ( X, Y : in std_logic; O1, O2, O3, O4 : out std_logic); end decode; architecture func of decode is begin O1 <= (not X) and (not Y); O2 <= (not X) and Y; O3 <= X and (not Y); O4 <= X and Y; end;

27. 27 Register A register is a device that stores a data word clk A B C D QAQA QBQB QCQC QDQD A four bit data register:

28. 28 Register in VHDL The same four bit register in VHDL looks like: library ieee; use ieee.std_logic_1164.all; entity Reg4 is port (DataIn: in std_logic_vector(3 downto 0); DataOut : in std_logic_vector(3 downto 0); C: in std_logic); end Reg4; architecture Behav of Reg4 is begin process (C) begin if (C = '1') then DataOut <= DataIn; end if; end process; end Behav;

29. 29 Using Xilinx ISE

30. 30 Constructing a Reg in VHDL Create a new source and assign the inputs and outputs:

31. 31 VHDL Form ISE will create this form:

32. 32 Final Code Enter the complete code:

33. 33 Simulating the code Create a new project – reg_tbw and set up the test inputs

34. 34 Run the Simulation Select execute

35. 35 Possible Quiz Remember that even though each quiz is worth only 5 to 10 points, the points do add up to a significant contribution to your overall grade If there is a quiz it might cover these issues: What is a MUX? What is a decoder? What is the purpose of an exit statement?