1. CALICE ECAL meeting VFE ASIC Next & next to next version 17 Janvier 2006, LAL Orsay

2. ECAL FEE The final ASIC :  System on Chip  Many different features  Many digital controls  Many functionnal blocks  32 to 256 channel/ASIC  Consumption : <100µW/Ch

3. Chip complexity ? FLC_PHY3 (4mm²) INTEL ® PENTIUM ™ IV (450mm²) ILC_FINAL (?mm²) ILC_PHY4 (6mm²)

4. Today status Starting point :  Physic prototype front-end electronic Available blocks :  Preamplifier  Charge Shaper  Analogue memory  Analogue idling mode  Bandgap voltage reference

5. Today status Blocks currently in design  ADC  Digital LVDS buffers  Fast shaper  Discriminator

6. Today status Proprietary 12 bit ADC High precision pulse generator for calibration 16 bits DAC  RF switch Digital state machine for subadressing  Digital memory  Bunch crossing ID counter  Subadress machine What is still missing :

7. ECAL FEE back-end It is time to think about FEE/DAQ interface ! Digital only Bus architecture for intra-slab data transfer Evoluted protocol  Reliability : what if a chip dies ? Where begin DAQ ? Where stop FE ?

8. Questions to (pre)answer today How to send data from the FE chip to the side of the slab ?  Token ring  Protocol  Data rates How to send slow control & calibration from the side of the slab ?

9. On chip formated data ADC result - 12 bit BCID – 12 bit Gain - 2 bit Channel nb - 6 bit Chip ID - x bit PositionEnergyTime  32bits / event without Chip ID

10. FEE I/O ports Only a few I/O  Due to the PCB design & the number of chips  Hopefully : low data rate (in the barrel…) Some numbers to keep in mind :  ~1800 ch/slab (1cm²)/ ~7200 ch/slab (.25cm²)  ~200 chips/slab (36ch/chip,.25cm²)  Occupancy : 5 hits/channel/train  Data rate calculation : 5*32*36=5.76kb/train/ASIC  28.8kb/s/ASIC 28.8kb/s*200=5.76Mb/s/Slab (720kB/s) We need to answer a question with MOKKA :  What is the mean number of hits on a slab during a train ?  …With different pad sizes

11. Time considerations time Time between two trains: 200ms (5 Hz) Time between two bunch crossing: 337 ns Train length 2820 bunch X (950 us) Acquisition 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) 1% duty cycle IDLE MODE 99% duty cycle 199ms (99%) Calibration ?

12. Chip I/O A proposal for the FE interface with DAQ :  3 CMOS (input)Subaddressing (slow) Idle mode, acquisition mode, A/D conversion mode, data transfer mode, slow control loading mode, calibration mode, …  1LVDS(input)Clock (fast)  1LVDS(input)Data IN (fast)  1LVDS(output)Data OUT (fast) 9 pins and it is the minimum ! Is it enough for a (safe) transfer protocol ?

13. Consumption Consumption will drive the size of the pads Can we go below the already challenging 100µW/ch ? What is the max pad size with 100µW/ch ?

14. DC coupling to the pad No HV capacitance on the 1*1cm pad Even less on a smalleer pad  Need to be DC coupled to the pad How to deal with a leaking pad ? We don’t want to loose the whole chip for that…

15. Outlook of urgent tasks Front-end  DC coupling (reliability issue) Back-end  DAQ interface description (today ?)  Data rate (today ?) Timing  Calibration, when ? Detector optim.  what consumption can we reach ? (let’s keep some safety contingency)  What is the induced pad size

16. Conclusion FE design :  In parallel front-end and back-end In french : mangeons la banane par les deux bouts

17. PCBs R&D

18. Design of ILC_FEV4 FLC_FEV1 FLC_FEV2 ILC_FEV3

19. Design of ILC_FEV4 Chip in the detector Thickness  Ultra-thin PCB  Chip burried in PCB FE chip (1mm) Wafer (500µm) PCB (600µm) 1750µm diodes+ FE electronic

20. What is missing in ILC_FEV4 Stitchable PCBs (no room for cables) PCB type 1 PCB type 2 PCB type 3 Glue ? Solder ? 1.5m

21. Schedule & Conclusions

22. Schedule Goal :  Having front-end electronics as close as possible from final detector electronics in the technological prototypes. Technological prototypes :  Funded by European research program (EUDET)  4-year program (2006-2009)  R&D on front-end electronic has to be over in 2008 to build the prototype before end of 2009

23. Conclusion Many R&D to be performed in a short time  FE chips  DAQ  PCBs Back-end FEE issue :  Same backend for all calorimeters to simplify DAQ

24. ANNEX

25. Schedule proposal

26. Real data rate ? 720kB/s / 0.25%=288MB/s during.5ms Where am I wrong ? That is 2.3 Gb/s That is the worst case (all cells fired 5 times) Only 576 Mb/s with 1*1cm cells We need to answer a question with MOKKA :  What is the mean number of hits on a slab during a train ?  …With different pad sizes