1. TRAMS PROJECT WP3 (T3.3) FP7 248789 PTC, November 4 th, 2011 Paul Zuber, Miguel Miranda Imec Acknowledgments: Pablo Royer, Peter Buchegger

2. WP3@Y2: Deliverable D3.5 D3.5: Report on the method that instantiates the monitor insertion in ASICs descriptions – Lead beneficiary: Imec – What: Monitor insertion flow – Input: RTL – Output: gate netlist with inserted monitor – Imec unit: PT – When: m24 – Status: Draft available 2

3. Two main types of low cost: Timing Monitors (Reactive) != Logic DFF clock G G O O R R T. Austin, D. Blaauw, T. Mudge, K. Flautner, “Making typical silicon matter with Razor”, IEEE Computer Society, Vol. 37, Iss.3, pp.57-65, March 2004.

4. != Logic DFF clock G G O O R R Sh Sh M. Eireiner, et al “ In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations ”, IEEE Journal of Solid-State Circuits, Vol.42, No.7, July 2007 Two main types of low cost: Timing Monitors (Proactive)

5. RTL2RTL Tool 5 Tool used by WL group Single Step RTL2RTL After Monitor insertion RTL-Netlist Monitor (knob) circuit in RTL Verify Re-use the original TestBenches Automated extended testing ~6 times slower than RTL Simulation ~7 times faster than post-synthesis simulation Selected Statistical Critical Paths SoC Design in RTL Synthesis and Place & Route Tool Properties Automated insert, connect, &route Single step before synthesis Builds on the top of standard existing tools: Tool in TCL Non invasive: no change in design interface Transparent to designer No design cost overhead No design cost It simply: WORKS! In silicon & simulation Naessens, F et al, "A 10.37 mm2 675 mW reconfigurable LDPC and Turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE," VLSI Circuits (VLSIC), 2010 IEEE Symposium on, vol., no., pp.213- 214, 16-18 June 2010

6. Monitors(Knobs) visible to system level OS Working toward proving its feasibility Reconfigurable SKM Hardware Controller on FPGA Synchronize circuitry Port (Multiplexed) LDPC Encoder Barrel Shifter(s) SoC Top-level 10.37 mm 2, 65nm FlexFec CMOS ASIC chip in testbed 103 Monitors: 103 Monitors: Area overhead: 0.144% of logic area, Power overhead is negligible @ system speed

7. First conclusions Monitor does not interfere “good” circuit operation Monitor does not complicate timing closure Monitor does not introduces design cost overhead Monitor does not required more design effort Monitor works: simulation and silicon 7 To controller Digital monitors in a chain

8. Back-up slides Miguel Miranda

9. Critical path selection Option 1: insert monitor after synthesis and P&R: – Timing closure gets jeopardized: no way out Option 2: Fully automated flow – Synthesis down to pre-layout netlist – Statistical timing analysis (could be based on VAM technology) – Selection of top X% statistically critical paths – Monitor insertion and re-synthesis (requires loop over synthesis) Option 3: Based on system knowledge of critical path -> e.g., barrel shifter of LDPC encoder which is in critical loop (1 cycle update operation) – requires system knowledge and limited manual intervention (list of RTL signals to monitor) Limited area overhead (<0.1%) shows list of considered monitors can 1000’s without noticeable impact – And the number of paths monitored per monitor is not 1 but many more 9

10. Delay Monitor (RTL description) 10