2. 1 AL and CA Lecture 13: System Design 1

3. 2 Outline System Level Design Control Signals Controller Design

4. 3 System Level Design

5. 4 GOAL: Illustrate the total design process VHDL to create a system (much like your microprocessor project) PROBLEM: Design a hardware stack using memory and a counter

6. 5 Stack Example Begin with a high level block diagram: Hardware Stack PUSH POP Reset CLK Data 8 TOP 8 err

7. 6 Hardware Stack Block The hardware stack will consist of three elements: Memory 8 words x 8 bits SP 3 bit counter Control Addr Data TOP PUSH POP Reset CLK err Control signals

8. 7 Control System

9. 8 Control Signals Given this system, what kind of control signals are required? Memory 8 words x 8 bits SP 3 bit counter Control Addr Data TOP PUSH POP Reset CLK err Control signals Read Memory Clear SP Count up Count down Write to Memory

10. 9 Signal Paths The control signals are distributed as: Memory 8 words x 8 bits SP 3 bit counter Addr Data TOP Control PUSH POP Reset CLK err r/w memclk Clear c_up ctclk Read Memory Clear SP Count up Count down Write to Memory

11. 10 Stack Pointer (SP) Design The SP is a simple up/down counter –3-bits (8 address values)

12. 11 Test SP It is important to test the operation of each subunit before assembling them into the final block. –Connect inputs and outputs to the SP

13. 12 Memory Block Design a VHDL Memory unit –8 words of 8 bits each

14. 13 Control System Design Based on the memory system, another control signal must be added to the control system: Memory 8 words x 8 bits SP 3 bit counter Addr Data TOP Control PUSH POP Reset CLK err r/w Clear c_up ctclk inclk outclk Also want to keep track of the size of the stack Stack_full Stack_empty

15. 14 VHDL Implementation The control system will be implemented using VHDL behavioral code: library ieee; use ieee.std_logic_1164.all; entity stackcontrol is port (push,pop,clk, reset : in std_logic; stack_full,stack_empty : in std_logic; clkct, inclk, outclk : out std_logic := '0' ; c_up, we,err,clear: out std_logic := '0' ); end stackcontrol; Control PUSH POP Reset CLK err we Clear c_up ctclk inclk outclk Stack_full Stack_empty

16. 15 State Machine Implementation The control system will be modeled as a state machine The VHDL architecture code will use a case statement in a process block We need to understand the operation of this stack in order to produce a state diagram which will be used to create the VHDL code

17. 16 Stack Operation The SP will point to the next open position in the stack –Hence a push operation will involve: Saving the data at the SP address Then, incrementing the SP –A pop operation will involve: Decrementing the SP Reading the data at the SP address SP PUSH 10 0 1 2 3 4 5 6 7 Stack 10 SP

18. 17 State Diagram Read Memory Decrement SP Increment SP Store data S0 S1 Push S2 Pop we S3 Stack_full Stack_empty err S5 inclk S6 inclk S7 we c_up S8 ctclk S9 ctclk c_up S4 Stack_full S10 Stack_empty ctclk S11 ctclk S12 we outclk S13

19. 18 VHDL Architecture 1 Start with the standard architecture definition –Also define the states architecture behave of stackcontrol is type statetype is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13); signal current : statetype := S0; begin process begin end process; end behave; Initial value of current No sensitivity list

20. 19 VHDL Architecture 2 process begin wait until clk = ‘1’; Instead of a sensitivity list case current is S0 err c_up when S0 => err <= 0; c_up <= 0; S1 push else if (pop = ‘1’) then current <= S2; else current <= S0; end if; if (push = ‘1’) then current <= S1; S2 pop when S3 => err <= ‘1’; current <= S0; S3 stack_full S4 stack_full when S1 => if (stack_full = ‘1’) then current <= S3; else current <= S4; end if; S10 stack_empty when S2 => if (stack_empty = ‘1’) then current <= S3; else current <= S10; end if; err

21. 20 VHDL Architecture 3 when S4 => we <= ‘1’; current <= S5; S0 err c_up S1 push S2 pop S3 stack_full S4 stack_full S10 stack_empty err S5 we S6 inclk when S5 => inclk <= ‘1’; current <= S6; S7 inclk when S6 => inclk <= ‘0’; current <= S7; S8 we c_up when S7 => we <= ‘0’; c_up <= ‘1’; current <= S8; S9 ctclk when S8 => ctclk <= ‘1’; current <= S9; ctclk when S9 => ctclk <= ‘0’; current <= S0; S11 ctclk when S10 => ctclk <= ‘1’; current <= S11; S12 ctclk we when S11 => ctclk <= ‘0’; we <= ‘0’; current <= S12; S13 outclk when S12 => outclk <= ‘1’; current <= S13; outclk when S13 => outclk <= ‘0’; current <= S0;

22. 21 Complete VHDL Code library ieee; use ieee.std_logic_1164.all; entity stackcontrol is port (push,pop,clk, reset : in std_logic; stack_full,stack_empty : in std_logic; clkct, inclk, outclk : out std_logic := '0' ; c_up, we,err,clear: out std_logic := '0' ); end stackcontrol; process begin wait until clk = ‘1’; case current is when S0 => err <= 0; c_up <= 0; else if (pop = ‘1’) then current <= S2; else current <= S0; end if; if (push = ‘1’) then current <= S1; when S1 => if (stack_full = ‘1’) then current <= S3; else current <= S4; end if; architecture behave of stackcontrol is type statetype is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11, S12,S13); signal current : statetype := S0; begin when S4 => we <= ‘1’; current <= S5; when S5 => inclk <= ‘1’; current <= S6; when S6 => inclk <= ‘0’; current <= S7; when S7 => we <= ‘0’; c_up <= ‘1’; current <= S8; when S8 => ctclk <= ‘1’; current <= S9; when S9 => ctclk <= ‘0’; current <= S0; when S10 => ctclk <= ‘1’; current <= S11; when S11 => ctclk <= ‘0’; we <= ‘0’; current <= S12; when S12 => outclk <= ‘1’; current <= S13; when S3 => err <= ‘1’; current <= S0; when S2 => if (stack_empty = ‘1’) then current <= S3; else current <= S10; end if; when S13 => outclk <= ‘0’; current <= S0; end case; end process; end behave; Need to be added later

23. 22 ModelSim Implementation

24. 23 Example Run

25. 24 Design Principles So far, the design of the hardware stack illustrates several design principles –These are useful for you when you approach your microprocessor design 1. Start with a high level block diagram and clearly label/understand all inputs/outputs 2. Break the problem down into smaller blocks 3. Design and test each block