1. 1 Design of Networks for Arithmetic Operations 2004.1.9 Kim jung kil

2. 2 순서 Simple serial adder State graphs Design of binary multiplier Design of signed binary multiplier

3. 3

4. 4 Control State of Serial Adder

5. 5 State Graphs for Control Networks X i X J /Z p Z q this means if inputs X i, X j are 1 (others : don't care), outputs Z p,,Z q are 1( others : 0 ) SkSk SpSp SqSq X1X1 X1'X2'X1'X2' X1'X2X1'X2 (X 1 ) (X 1 ' X 2 ) = 0 X 1 + X 1 ' X 2 ' + X 1 ' X 2 = 1

6. 6 Design of a Binary Multiplier

7. 7 Block Diagram for Binary Multiplier

8. 8 Multiplication example

9. 9 State Diagram of Binary Multiplier S9 S8 S6 S7 S5 S3 S1 S2 S4 S0 St ' /0 St/Load M/Ad _/Sh M ' /Sh _/Done

10. 10 begin process begin wait until Clk= '1'; case state is when 0=> if St='1' then ACC(8 downto 4) <= "00000:; ACC(3 downto 0); <= Mplier; State <= 1; end if; when 1|3|5|7 => if M='1' then ACC(8 downto 4) <= add4(ACC(7 downto 4),Mcand,'0'); State = State +1; else ACC <= '0' & ACC(8 downto 1); State <= State + 2; end if;

11. 11 when 2|4|6|8 => ACC <= '0' & ACC(8 downto 1); State <= State + 2;; when 9 => State <= 0; end case; end process; Done <= '1' when State = 9 else '0'; end behave1;

12. 12 Counter 를 이용한 설계

13. 13 State Graph for add-shift control

14. 14 Design of Signed Multiplier 0.111 (+7/8) X 0.101 (+5/8) (0.00)0111 (+7/64) (0.)0111 (+7/16) 0.100011 (+35/64) 0.101 (+5/8) X 1.101 (-3/8) (0.00)0101 (+5/64) (0.)0101 (+5/16) (0.)011001 1.011 (-5/8) 1.110001 (-15/64) 1.101 (-3/8) X 0.101 (+5/8) (1.11)1101 (-3/64) (1.)1101 (-3/16) 1.110001 (-15/64) 1.101 (-3/8) X 1.101 (-3/8) (1.11)1101 (-3/64) (1.)1101 (-3/16) 1.110001 0.011 (+3.8) 0.001001 (+9/64)

15. 15 Block Diagram for Signed Multiplier A(accumulator)B CONTROLCONTROL Load Sh Ad Done St Cm multiplier multiplicand M product 4-bit full adder C in 1's complementer Cm

16. 16 State Diagram of Signed multiplier S0 S5 S4 S1 S2 S3 St'/0 St/Load M/AdSh M'/Sh M/CmAdSh M'/Sh M/AdSh M'/Sh M/AdSh M'/Sh _/Done

17. 17 2’s Complement multiplier Begin process variable addout : bit_vector(4 downto 0); begin wait until Clk= '1'; case State is when 0=> if St='1' then A <= "0000"; B <= Mplier; State <= 1; end if

18. 18 2’s Complement multiplier( 계속 ) when 1|2|3 => if M= '1' then addout := add4(A,Mcand,'0'); A<=Mcand(3) & addout(3 downto 1); B<=addout(0) & B(3 downto 1); else A<=A(3) & A(3 downto 1); B<=A(0) & B(3 downto 1); end if; State <= State +1;

19. 19 2’s Complement multiplier when 4 => if M='1' then addout := add4(A,not Mcand,'1'); A<=not Mcand(3) & addout(3 downto 1); B<=addout(0) & B(3 downto 1); else A<=A(3) & A(3 downto 1); B<=A(0) & B(3 downto 1); end if; State <= 5; when 5 => State <= 0; Done <= '0';

20. 20 End Q/A