1. SOC&VLSI RAM and Memory Controller Peiyuan Wang 4/21/2011

2. I NTRODUCTION Multi-processor network system Memory is used to store data and program. Processor realizes calculation by fetching instructions, decoding and executing. Memory controller as a block connecting processor and RAM contains the logic necessary to read and write to RAM. In our system, totally 32K byte memory is used for one node. For our project, memory controller also works kind of like an arbiter for loading program.

3. N ODE B LOCK D IAGRAM http://kona.ee.pitt.edu/socvlsi/doku.php?id=node_design

4. SOC P ART AMBA 3 AHB-lite protocol Memory Generator Memory Controller Design Processor, Memory controller, Memory Integration Test and Debug

5. D ECODER B LOCK D IAGRAM Processor reads whole word and decides which part to use Processor HWDATA is always 32bits, memory should know how many bytes and which bytes to write. Decoder should give Test Bench access to load program.

6. D ECODER T RUTH T ABLE LOADDTRANSDWRITEDSIZE [1:0] DADDR [1:0] WEN1*WEN2WEN3WEN4 010100 1110 010100011101 010100101011 0 100110111 010101001100 010101100011 0 1 000000 1Ignore 0000 Other combinations 1111 *WEN in RAM is active low.

7. D ECODER F UNCTION Translate AHB bus signals to select different RAM cell Realize LOAD, WRITE byte, half word, word function

8. RAM B LOCK D IAGRAM * CEN is tied to low all the time. TSMC 130nm Process High-Speed Synchronous Single-Port SRAM

9. RAM T IMING Read-cycle TimingWrite-cycle Timing All setup time and hold time should be satisfied. If not, failure write and/or read

10. C ONTROLLER _RAM B LOCK D IAGRAM CLK A D CEN WEN Q DCLK DADDR DTRANS DWRITE DSIZE DWDATA LOAD WEN1 WEN2 WEN3 WEN4 CLK A D CEN WEN Q CLK A D CEN WEN Q CLK A D CEN WEN Q WEN1 WEN2 WEN3 WEN4 DADDR [31:0] DCLK LOAD LOADADDR [31:0] LOADDATA [31:0] DWRITE DTRANS [1:0] DSIZE [1:0] DWDATA [31:0] RAMEN DCLK DADDR DTRANS DWRITE DSIZE DWDATA LOAD DCLK WRITEDATA1 DECODER RAM1 RAM2 RAM3 RAM4 WRITEDATA2 WRITEDATA3 WRITEDATA4 RAMADDR RAMEN RDATA [7:0] RDATA [15:8] RDATA [23:16] RDATA [31:24] RDATA RAMADDR

11. C ONTROLLER _RAM Control data flow Adjust the AHB “address phase”, “data phase” timing to RAM timing Adjust Test Bench “load mode” to RAM timing Synchronize both mode Use load signal to decide which address and data to pass

12. P ROCESSOR, M EMORY C ONTROLLER, M EMORY I NTEGRATION AND T EST CPU Controller _RAM RAM.bin Test Bench LOADADDR LOADDATA AHB RDATA Processor Other signals

13. LOAD MODE & CPU MODE LOAD mode CPU mode(AHB)

14. T EST (“ HELLO WORLD ”)

15. C ONSOLE

16. A CHIEVEMENT Get familiar with ARM AMBA bus protocol Learn memory mapping Design soft IP block for certain customed request Detailed interrelation between Processor and Memory

17. VLSI PART Process to create integrated circuit Design Compiler: generate gate-level netlist Encounter (Place and Route): generate layout

18. C ONTROLLER _RAM @ 90MH Z Critical Path(RAM  RDATA) Time slack: 3.93ns Reason: RAM block constrain the timing

19. L AYOUT I NTEGRATION Layout area: 1342389 nm 2

20. N ON -V IOLATION R EPORT

21. P OST _PR S IMULATION Note: Processor is behavioral model Print “hello world” in post_PR sim

22. C ONCLUSION Memory controller can achieve read and write to 4 memory banks. It can follow processor’s request to do certain byte, half word, word write. It can offer data back to processor in time. It can load program and reset memory state. Memory and memory controller design can be integrated with other block(Processor) and can function correctly in both CPU mode and LOAD mode. Post PR, Controller_RAM can run at 90MHz with no violations.

23. A CKNOWLEDGEMENT Dr Jones and Dr Levitan for guidance Xiang Chen for layout Mike Rogers for SDF solution Classmates for help If any questions regarding memory and memory controller, please contact me(wap15@pitt.edu)

24. Thank you