1. Spring 2006 1 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Advanced Computer Architecture Lecture 4 Project 1 reviews CPU controller design Slave bus agent

2. Spring 2006 2 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Project 1 team reviews Team Cat Team Dog

3. Spring 2006 3 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering CPU block diagram PCROM FSM Tri-State Buffer Breq Inta Bgnt Ack Int CADCAD Note: no data read into CPU

4. Spring 2006 4 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering CPU schematic

5. Spring 2006 5 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering FSM design Assume: sequential solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options   

6. Spring 2006 6 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Full state diagram b a c d f g h e i l jk Reset nop Bgnt Ack Breq Breq, Ben Int Inta Reset Count

7. Spring 2006 7 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering FSM design Assume: sequential solution Describe: what your design should do Determine: inputs and outputs Create: state diagram Assign: adjacent states (no glitches) Prepare: next state table Explore: implementation options     Delay this until next project

8. Spring 2006 8 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Find next state table? Partial Table ONLY

9. Spring 2006 9 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Project 2 overview Objective: design the CPU model controller State diagram: provided in class State table: provided in class State assignments: must be adjacent Next state decoder and output decoder: your choice of implementation

10. Spring 2006 10 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Project 2 trace a b c d e f g b

11. Spring 2006 11 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Project 2 trace, continued. b ijkl g h

12. Spring 2006 12 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering System view of a computer ··· Signal 0 Signal n Agent 0 Agent n ··· Bus Agents communicate across a bus 

13. Spring 2006 13 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Agents Goal: perform some function (memory, I/O, etc.) Types –Master –Slave Operations –Memory or I/O space –Read or write –Interrupt

14. Spring 2006 14 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Agent requirements Master Request bus, acquire bus, drive bus, wait for agent to respond, check for interrupts Slave Check address bus, decode control bus, possibly drive data bus, acknowledge completion, possibly request an interrupt

15. Spring 2006 15 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Master agent: CPU model PCROM FSM Tri-State Buffer Breq Inta Bgnt Ack Int CADCAD Note: no data read into CPU

16. Spring 2006 16 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Slave block diagram Decode Data Source Data Sink Tri State A C D Ack LS138LS244 Device

17. Spring 2006 17 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Decoding Inputs –Address bus –Control bus Fully decoded: unique address/function found Implementation (LS138) –Two levels: address, control –Use output of first level to enable second

18. Spring 2006 18 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Decoding block diagram LS138 A C Correct address Correct address and function First and second level may be reversed

19. Spring 2006 19 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Fully decode I/O write to 0xf ?

20. Spring 2006 20 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering

21. Spring 2006 21 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Find next state table? Partial Table ONLY

22. Spring 2006 22 EE 437 Lillevik 437s06-l4 University of Portland School of Engineering Fully decode I/O write to 0xf ?