1. Spring 2006CSE 597A: Analog-Digital IC Design Scan-Flash ADC Low Power, High-Throughput AD Converters Melvin Eze Pennsylvania State University eze@cse.psu.edu

2. Spring 2006CSE 597A: Analog-Digital IC Design Outline ADC Converters Flash ADC Scan-Flash Architecture Target Specifications Schedule References

3. Spring 2006CSE 597A: Analog-Digital IC Design Analog-Digital Converters DSP is really wonderful but… Real World Signals are Analog: –Continuous time –Continuous amplitude DSP can only process: –Discrete time –Discrete amplitude Need for data conversion from Analog to Digital and back Analog Pre-Processing A/D Conversion DSP D/A Conversion Analog Post-Processing Filters ? 000..001.. 011 ? Filters Analog Output Analog Input Slide Adapted from: Haideh Khorramabadi EE247 Class Slides

4. Spring 2006CSE 597A: Analog-Digital IC Design Example: A typical Cell Phone Slide Adapted from: Haideh Khorramabadi EE247 Class Slides Contains an Integrated form of: 4 Rx Filters 4 Tx Filters 4 Rx ADCs 4 Tx DACs 3 Auxiliary ADCs 8 Auxiliary DACs

5. Spring 2006CSE 597A: Analog-Digital IC Design Flash ADC

6. Spring 2006CSE 597A: Analog-Digital IC Design Scan-Flash ADC Encoding Logic Switch Control Logic EN High frequency clock V REF V IN Additional Features Switched Input Multi-cycle latching of Thermometer code Minimum effect on C IN Control Logic is Shift-Register based

7. Spring 2006CSE 597A: Analog-Digital IC Design Scan-Flash ADC Encoding Logic Switch Control Logic EN High frequency clock V REF V IN Scan Techniques for B-bit ADC Linear Scan [O(2 B )] Very Simple but very inefficient Binary Tree Scan [O(B)] Very efficient but tough to implement so far Linear Window Scan [O(K)] K > B, but be implementation characteristics

8. Spring 2006CSE 597A: Analog-Digital IC Design K_Scan-Flash ADC Encoding Logic Switch Control Logic EN High frequency clock V REF V IN_K Switch Control Logic V IN_2 Switch Control Logic V IN_1 K stages

9. Spring 2006CSE 597A: Analog-Digital IC Design Target Specifications 2 Channels [2-Scan-Flash ADC] 12 bit per channel Power Supply: 5V Power Consumption: 400 mW DNL/INL: 1 LSB Area: 1mm 2 Speed: 50 MSPS per channel (100 MSPS aggregate) Operating Frequency: 100MHz

10. Spring 2006CSE 597A: Analog-Digital IC Design Schedule Week 1: Specifications and Initial Simulations Week 2: Complete SPICE Implementation of Switch Week 3: Complete Verilog Implementation of Digital Control Week 4: Schematic Layout of single channel SCAN-FLASH -no ROM in Cadence Schematic Editor Week 5: Begin Module layout in Virtuoso and SPICE simulations Week 6: More Layout Week 7: Complete Layout Week 8: Full System test and Performance Analysis Week 9: Debug and Complete

11. Spring 2006CSE 597A: Analog-Digital IC Design References