1. MADEIRA Valencia report V. Stankova, C. Lacasta, V. Linhart Ljubljana meeting February 2009

2. Content ● Our objective for 2009 ● Introduction of the DAQ system ● Introduction of the Mother Board ● Where we are and what we are working on ● Next steps

3. Our objective for 2009 ● The idea is to be design a acquisition system which will handle a probe with a 8 layers. Each layer has two sensors. ● Each senor represents an “entry” for the DAQ system MB Probe with 8 layers

4. Introduction DAQ system ● Each sensor is composed of two DBs so each sensor will have “two cables”, one per hybrid, so it will represent 2 entries in the DAQ system

5. The Mother Board The MB will include different hardware blocks which will be responsible of: The control of the hole system The synchronization of the system The communication with PC The configuration of the readout chips Control the acquisition process The storage of the data The main component of the DAQ system is the MB ● The MB will be able to attend 16 DB, each one can held up to 16 ASIC's from the VATAGP* family

6. Inside of the FPGA FPGA task Synchronization of the hole system DACs and ADCs configuration Will implement a Time Sampling Block with a resolution of ~1 ns Generate calibration pulses Generate software trigger The main component of MB is the FPGA

7. The trigger block Software trigger – useful for pedestal runs External trigger – trigger from the second detector Internal trigger – trigger from the DBs Coincidence – this trigger signal is generated when there are external and internal trigger inputs.

8. The DAQ block

9. The ADC chip ADC chip AD9222 from Analog Devices 12-Bit, 40 MSPS 8 ADCs integrated into 1 package 2 V p-p input voltage 1.8 V supply operation Serial port control (SPI) Serial LVDS signal output A data clock output (DCO) operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation.

10. The FPGA chip For FPGA chip selection we have consider: The number of IO pins We need ~ 50 FPGA pins per DB TOTAL ~800 pins for 16DBs The number of integrated RAM block ( needed to implement FIFOs inside the FPGA The logic cells The price Our choice Spartan 3 from Xilinx Signals transfer between DB & MB

11. Doing things in Valencia Represent the DAQ system using evaluation boards Evaluate the chosen components like ADC, DAC and FPGA Design and manufacturing of the two connection boards. Programing the FPGA

12. Doing things in Valencia ● First test of communication with external devices like ADC chip ● Program the ADC (AD9222) chip using the SPI bus ● Test to obtain digital data using an external test pulse from the ADC evaluation board ● Take 5 samples of each analog data and calculate the average value

13. Next steps ● Connect the VaTa2 intermediate board with EBS3 ● Program the FPGA to configure the ASIC and generate the readout sequence ● Test: ● The analog/digital conversion with real detector signals ● The acquisition rate ● The processing of captured data ● Ethernet data transfer

14. Thank you for your attention Any suggestions or comments are welcome...

16. Backup

17. With intermediate board or without?

18. The DAQ block

19. VaTa2 connection board DAC space