1. February 1, 2011GT20101 Multicore SoC Architecture and Prototyping for Parallel ECG Processing s1150072 Yumiko Kimezawa Supervised by Prof. Abderazek Ben Abdallah Adaptive Systems Laboratory, The University of AIZU, Japan

2. Outline Background Proposed new system architecture Evaluation methodology Hardware complexity and processing results Conclusion Future work February 1, 2011GT20102

3. Background February 1, 2011GT20103 ECG is used for diagnosis of heart disease Previous system processes the ECG signals from single lead only at a time Figure: Previous system architecture proposed last year single lead PPD Algorithm ADC 1 ADC 12 FIR 1 FIR 12 Buffer ECG Signal Analysis 1:Signal reading 2:Filtering3:Analysis4:Display 12 leads External Memory Patient: A P = # mV Q = # mV R = # mV S = # mV T = # mV U = # mV Interval = # ms

4. PPD Algorithm study (1/2) February 1, 2011GT20104 Period-Peaks Detection (PPD) Algorithm Figure: A typical ECG graph

5. PPD Algorithm study (2/2) February 1, 2011GT20105 Period detection Peaks processing Data reading Derivation Autocorrelation Finding interval Extraction Store of results Discrimination

6. Problems with previous system February 1, 2011GT20106 Previous system can not process ECG signals from multiple leads at a time Not high performance

7. My research and goal Study of SW and HW architecture of single lead SoC Proposal, design and evaluation of a new multicore system for multi-lead processing February 1, 2011GT20107

8. Previous system architectu re February 1, 2011GT20108 Raw ECG Data ROM External Memory External Memory Graphic LCD Controller Slave CPU Slave CPU Slave CPU Memory Timer Master CPU Memory Master CPU Memory Master CPU Master CPU Timer Shared Memory Shared Memory FIR Filter Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module : Data flow : Control signal : Data flow : Control signal LED Controller LED Controller Avalon Bus

9. Proposed new system architectur e February 1, 2011GT20109 Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module : Data flow : Control signal : Data flow : Control signal LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU Slave CPU Raw ECG Data ROM External Memory External Memory Shared Memory Shared Memory

10. 12 sample data were used for evaluation -from MIT-BIH Normal Sinus Rhythm Database 12 sample data were processed as below -In the single lead system, one sample data 12 times serially -In the 2-lead system, two sample data 6 times serially -In the 3-lead system, three sample data 4 times serially Comparison of the total time spent on processing of 12 sample data between each system February 1, 2011GT201010 Evaluation methodology

11. Hardware complexity February 1, 2011GT201011 System model Logic utilizationBlock memory bitsFmax (MHz) Power (mW) Combinational ALUTs Memory ALUTs Dedicated Logic registers Total 1-lead9,7761611,69615%1,223,688(22%)96.43621.53 2-lead17,3253221,39327%2,351,368(42%)132.49627.23 3-lead24,8634831,08838%2,954,504(52%)119.42632.41 Target device: Stratix III DSP board EP3SL150F1152C2 The rate of logic utilization had increased in proportion to the number of leads

12. Processing results February 1, 2011GT201012 1-lead2-lead3-lead 16256 13.302s 14.858s 17.711s 16273 10.628s 16420 12.845s 14.298s 16483 12.441s 18.238s 16539 11.582s 13.161s 16773 11.107s 16786 11.106s 14.063s 14.009s 16795 8.739s 17052 10.795s 12.050s 17453 10.254s 17.941s 18177 11.476s 14.708s 18184 10.229s Total134.504s 83.138s 67.899s Record No. Archi- tecture

13. Processing results February 1, 2011GT201013 1-lead2-lead3-lead 16256 13.302s 14.858s 17.711s 16273 10.628s 16420 12.845s 14.298s 16483 12.441s 18.238s 16539 11.582s 13.161s 16773 11.107s 16786 11.106s 14.063s 14.009s 16795 8.739s 17052 10.795s 12.050s 17453 10.254s 17.941s 18177 11.476s 14.708s 18184 10.229s Total134.504s 83.138s 67.899s Record No. Archi- tecture Decrease 38%

14. Processing results February 1, 2011GT201014 1-lead2-lead3-lead 16256 13.302s 14.858s 17.711s 16273 10.628s 16420 12.845s 14.298s 16483 12.441s 18.238s 16539 11.582s 13.161s 16773 11.107s 16786 11.106s 14.063s 14.009s 16795 8.739s 17052 10.795s 12.050s 17453 10.254s 17.941s 18177 11.476s 14.708s 18184 10.229s Total134.504s 83.138s 67.899s Record No. Archi- tecture

15. Processing results February 1, 2011GT201015 1-lead2-lead3-lead 16256 13.302s 14.858s 17.711s 16273 10.628s 16420 12.845s 14.298s 16483 12.441s 18.238s 16539 11.582s 13.161s 16773 11.107s 16786 11.106s 14.063s 14.009s 16795 8.739s 17052 10.795s 12.050s 17453 10.254s 17.941s 18177 11.476s 14.708s 18184 10.229s Total134.504s 83.138s 67.899s Record No. Archi- tecture Decrease 50%

16. Conclusion February 1, 2011GT201016 Parallel processing of the ECG signals from 2-lead and 3-lead Processing time in the 2-lead system was about 38% less than in the single lead system Processing time in the 3-lead system was about 50% less than in the single lead system

17. Future work PPD modules will be divided into some tasks and these tasks will be mapped to many cores. PPD algorithm will be optimized by using OpenMP or MPI to parallelize the C code and test it in the multicore system. February 1, 2011GT201017

18. February 1, 2011GT201018 Thank you for listening