1. 4/11/2005 Applied Logic & Computation for System Design - An introductory invitation Jie-Hong R. Jiang 江介宏 National Taiwan University

2. Science & engineering System design is both a scientific and an engineering task Science Discovering hidden truths of natural/artificial systems (in theory) Engineering Searching effective solutions to optimization problems (in practice)

3. Interdisciplinary study System design maps computation tasks to physical systems Computer science Automata and logic Algorithms and complexity Electrical engineering Circuits and systems Control and communication Physics

4. Logic? Reason! Logic is the foundation of math Math is the foundation of science Logic is the foundation of science Aristotle (384-322 B.C.)

5. Applied logic? Reason the correctness of the constructed systems Demonstrating the absence or existence of some properties in a design A silly bug (big bang - present)

6. Computation? Logic in action! Charles Babbage (1791-1871)

7. Applied Computation? Analyze, optimize, and verify the designed systems

8. System modeling Models of computation Classical systems FSMs, timed/hybrid automata, Petri nets, dataflow process network, etc. Quantum systems Hamiltonian formulation of quantum computation − Perturbation theory and quantum search

9. System synthesis Closing the gap between synthesis and verification Certificate synthesis tools Breaking the infinite loop between synthesis and physical design Design closure Design in uncertainty Statistical optimization Interface/unknown component synthesis System Level Register Transfer Level Gate Level Transistor Level Layout Level Mask Level

10. System analysis Timing/power analysis Efficient FSM initialization FSM composability analysis

11. System verification Invariant verification of systems under specialized transformations Reduction techniques Property-dependent abstraction/refinement Similarity exploitation RTL decision procedures SAT extensions Conformance checking between different design levels Transaction level to register transfer level conformance checking RTL to gate level equivalence checking

12. For more info http://cc.ee.ntu.edu.tw/~jhjiang (warning: under construction)