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The AGET chip Circuit overview, First data & Status
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Outline Architecture & operation phases of the chip,
The SCA readout mode, Charge Channel: linearity & resolution, Architecture of the Trigger, Some data: transfer function, threshold value, … Hit channel register: protocol of the write & read, Schedule (Asic submission).
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AGET: Architecture AGET Slow Control. Power on reset. Test mode:
Serial Interface Mode CK In Test CSA;CR;SCAin (N°1) Asic “Spy” Mode Readout SCA MANAGER SLOW CONTROL W / R TEST Power on Reset [+ indisc] AGET 512 cells SCA FILTER tpeak CSA 1 channel x72in ADC Charge range DAC Discri inhibit BUFFER x76 Hit register Σ 72 discri. SCAwrite Trigger pulse Slow Control. Power on reset. Test mode: calibration or test [channel/channel] functional [72 channels on one shot] Spy mode (cx 1). 12-bit ADC [ADS6422] Main features for AGET 72 Analog Channels: Analog part + Sampling Capacitor Array. Main features for the channel Input Current Polarity: positive or negative. CSA + PZC + Filter (semi-Gaussian order 2). [Possibility to bypass the CSA]. SCA: 512 analog memory cells [new!! + 1 for internal logical operation facility]. Auto Triggering: discriminator + threshold (DAC) + inhibition. Main features for the readout Trigger[ Analog OR of the 72 discri. ] & SCA analog data => Same ADC channel. 4 SCA readout modes. Address of the hit channel(s) [read & write].
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AGET: Mode of operation
Asic management SCA read: READ & CKread SCA write: Write & CKwrite Slow control: Din, Dout, CK, CS Test: Pulser (Iinj or Vinj) Analog Data Conversion (Trigger & CSA analog data) ADC & Pulser: AsAD card AGET 512 cells SCA FILTER tpeak CSA 1 channel x72in 76 Charge range DAC BUFFER SCA MANAGER SLOW CONTROL TEST W CKw R CKr Din CK Dout Cs Iinj Vinj Discri inhibit Hit register Σ 72 discri. SCAwrite Trigger pulse Discri_in Discri_out Hit_channel Trigger_out Write_SCA Read_Address_hit channel Data_ADC_in Read_SCA Data_SCA_out SCA_in Channel i Stop Sampling: on external or local Trigger SCA write address read SCA read CSA_in Trigger SCA data
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AGET: SCA Analog Memory:
72 channels + 4 dummy channels [for common mode or Fix pattern noise rejection purpose]. Write: 1MHz to 100MHz Read: 25MHz SCA Manager SCA write 76 lines 512 cells SCA read Clk write Clk read R In Bufferout W CLKwrite CLKread Write Read Write phase Read phase c0 c511 c510 ci-2 c1 c. ci ci-1 ci+1 ci+2 Peaking Time: 100ns SCA: circular memory Results obtained on AFTER chip
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AGET: SCA Read Phase Channel Readout mode : all channels; hit channels or specific channels Read_SCA CKR_SCA Data_SCA_out 9xTrck 61xTrck Address of the last Column read Column n+511 address Vlow Vreset Column n 3xTrck 76xTrck C0 C1 C75 510x3xTrck + 510x76xTrck Column n+1 lumn n+511 Column n c0 c511 c510 ci-2 c1 c. ci ci-1 ci+1 ci+2 Channel 0 Readout Time: 512x [n channel + 3]xTrck + 79xTrck = 64.6 µs µsxnchannel [Trck = 40 ns] . n = 1 channel => Readout time = µs. . n = 10 channels => Readout time = µs. . n = 36 channels => Readout time = 801 µs. . n = 76 channels => Readout time = ms. c0 c511 c510 ci-2 c1 c. ci ci-1 ci+1 ci+2 Channel 2 c0 c511 c510 ci-2 c1 c. ci ci-1 ci+1 ci+2 Channel n c0 c511 c510 ci-2 c1 c. ci ci-1 ci+1 ci+2 Channel 75
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AGET: SCA Read Phase SCA readout mode: 512, 256 or 128 analog memory cells / channel 512 analog memory cells / channel: Write phase Stop (trigger) ci+1 Write phase: Tdrift ≤ 512 / Fsampling Read phase: SCAcells = 512 511 ci Readout phase 256 analog memory cells / channel: Write phase Stop (trigger) Write phase: 2 x Tdrift ≤ 512 / Fsampling Read phase: SCAcells = 256 511 ci Readout phase Internal Logical Operation 128 analog memory cells / channel: Write phase Stop (trigger) Write phase: 4 x Tdrift ≤ 512 / Fsampling Read phase: SCAcells = 128 511 Readout phase
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pole zero cancellation
AGET: Charge Channel SCA level: 3 Charge ranges; 2 bits register / channel: 120 fC or 1 pC or 10 pC or CSA standby[+ PZC filter]. PZC level: zero: 50 µs; Pole: 25ns to 500ns. RC2 level: Pole: 25 ns to 500 ns. Bypass: bypass: [CSA+PZC] or [CSA+PZC+RC2]; 2 bits global register + individual standby CSA. Peaking Time: 50ns to 1µs in Cl Cdet Cg2 + - 2*Cg2 Gain-2 RHV vdc Cs Sallen&Key Filter 16 values Cg 2*Cg pole zero cancellation Cp Rp standby s3 s4 s5 Slow Control Register [channel level] Decoding s0 2 s1 s2 [Asic level] Enable CSA Cf0 Rf0 Cf1 Rf1 Cf2 Rf2 Cf0: 100 fF Cf1: 1 pF Cf2: 10 pF VCSAoutput: 1V Cp: 1.8 pF Rp: 28 MΩ Cs: 1 pF Rs: 25 kΩ to 500 kΩ
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AGET: Charge Channel Some numbers: Simulation results
I.N.L: Charge range: 10pC; Peaking time: 50ns & 100ns; Input signal polarity.
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AGET: Charge Channel Some numbers: Simulation results
Charge resolution: versus input capacitor and peaking time
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AGET: Charge Channel Some numbers: Simulation results
Charge resolution: versus input capacitor and peaking time
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AGET: Charge Channel Some numbers: Simulation results
Charge resolution: versus input capacitor and peaking time
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AGET: Charge Channel Some numbers: Simulation results Peaking Time:
twhm Tpeak5%100% Tpeak100%5% Some numbers: Simulation results Peaking Time:
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AGET: Trigger channel Discriminator Architecture: L.E.D
Threshold value: Tunable; Global DAC [3 bits + polarity bit] + individual DAC [4 bits] 3-bit DAC 4-bit Discri + - Sign Polarity Signal over threshold Gain Common to all channels Slow Control Register [channel level] 4 inhibit FILTER CSA PZC G2 512 cells SCA Input Dynamic range: 5 % of channel input charge range Peaking Time: 50 ns to 1 µs [same filter than charge channel]
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AGET: Trigger channel Some numbers: Simulation results
Threshold value: Tunable; Global DAC [3 bits + polarity bit] + individual DAC [4 bits] Charge Range 120fC 1pC 10pC DAC lsb 293 eV 2.7KeV 27KeV Maximum threshold value 37KeV 343KeV 3.43MeV
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AGET: Trigger channel Some numbers: Simulation results
Minimum Threshold value: 120fC range
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AGET: Trigger channel Some numbers: Simulation results
Minimum Threshold value: 1pC range
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AGET: Trigger channel Some numbers: Simulation results
Minimum Threshold value: 10pC range
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AGET: Trigger channel Trigger Architecture: Analog sum of the 72 discriminator outputs => Multiplicity Phase: synchronous of the ckADC signal & active during SCA writing phase Width: 2 x T ckADC (80ns) Dead Time [to avoid ringing]: any, fixed value (4µs +/- 1.5µs) or hit-channel register discri threshold Vin + - disc_out Set Q Reset width Memory In Synchro & Width (2*TSCAckread) Channel (4µs) veto trigger Hit-channel register 4µs Slow control Itrigger x 72 Current Voltage SCA_write ADC BUFFER ckADC SCA_read SCA_data AGET 1 Discri_in Disc_out Memory veto ckADC trigger width
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AGET: Trigger channel Trigger signal:
Transfer function: 20.5mV / hit channel at +/- 6% [ 42 ADC lsb at +/- 2 ] ADC input dynamic range Resolution: Hit channel number Noise 0.68 lsb 1 16 0.70 lsb 72 0.72 lsb
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AGET: Trigger channel Trigger signal: Rise Time (1%_99%): 18ns
Fall Time (99%_1%): 19ns One hit channel 72 hit channels
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AGET: Hit channel register
Phase: Discriminator output [rising edge of the Time over threshold signal] Width: 1 complete SCA sampling time < Width < 2 complete SCA sampling time Multiple hit event: Yes (2) [the width will be extended to 1 complete SCA sampling time] Discri_in Disc_out hit1 hit2 SCAcell0 Hit_channel SCA_write SCA_read 512*TSCAwck 1 event 2 events SCA read phase
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AGET: Hit channel register
Hit channel register & selective channels read out Concept: To keep the same pin in / pin out of the chip [no additional signals] Idea: To re-use the slow control link in a “fast” mode [25 MHz] X 1 XXXXX Sc_din Sc_ck Sc_en Sc_dout 72xTck SCA_read Read operation SCA_write Hit channel register <71 :0> This solution must be validated by: AsAd, CoBo and MUTANT idle X Sc_din Sc_ck Sc_en Sc_dout 72xTck XXXXX SCA_read Write operation SCA_write Read channel address <0 :71>
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AGET: Requirements Parameter Value Polarity of detector signal
Negative or Positive Number of channels 72 External Preamplifier Yes; access to the filter or SCA inputs Charge measurement Input dynamic range 120 fC; 1 pC; 10 pC Gain Adjustable/(channel) Output dynamic range 2V p-p I.N.L < 2% Resolution < 850 e- (Charge range: 120fC; Peaking Time: 200ns; Cinchannel. < 30pF) Sampling Peaking time value 50 ns to 1 µs (16 values) Number of SCA Time bins 512 [new] Sampling Frequency 1 MHz to 100 MHz Time resolution Jitter 60 ps rms Skew < 700 ps rms Trigger Discriminator solution L.E.D Trigger Output/Multiplicity OR of the 72 discriminator outputs (pulse of 2*TckADC) Dynamic range 5% of input charge range < 5% Threshold value 4-bit DAC/channel + (3-bit + polarity bit) common DAC Minimum threshold value ≥ noise Readout Readout frequency 20 MHz to 25 MHz Channel Readout mode Hit channel; specific channels; all channels SCA Readout mode 512 cells; 256 cells; 128 cells Test calibration 1 channel / 72; external test capacitor test 1 channel / 72; internal test capacitor (1/charge range) functional 1, few or 76 channels; internal test capacitor/channel Counting rate < 1 kHz Power consumption < 10 mW / channel
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AGET: Schedule Remaining Job: AMS technology run schedule:
Hit channel register: read & write protocol SCA readout: global schematic AGET: global schematic [channel level; all the chip] AGET: global layout AMS technology run schedule: 29 May / 20 July / 14 September / 7 December 2009
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