1. 2008-11-20E. Hazen1 Fermilab CMS Upgrade Workshop November 19-20, 2008 A summary of off-detector calorimeter TriDAS electronics issues Eric Hazen, Boston University On behalf of my ECAL and HCAL colleagues

2. 2008-09-17E. Hazen2 Outline Calo TriDAS upgrade goals and constraints Review of HCAL and ECAL off-detector electronics Hardware Upgrade Options Summary of Options Upgrade ”Scenario I” Selective Readout Review current ECAL scheme Possible combined schemes DAQ Path Issues Staging options, compatibility with existing system Summary

3. 2008-11-20E. Hazen3 Calo TriDAS Upgrade Goals Necessary: HCAL front-end changes Channel count, TDC data, etc ECAL+HCAL: DAQ hardware changes, Lumi increase... more BW ECAL+HCAL: Trigger – RCT opto inputs, architecture changes? Desirable: DAQ: common local/global readout path Combine ECAL and HCAL in common hardware ($$$ savings?) Provide for combined selective readout of ECAL and HCAL Data compression in DAQ path Provide more FPGA resources for calo trigger near detector Comply with enforced or de-facto CMS standards … others?

4. 2008-11-20E. Hazen4 Calo TriDAS Upgrade Constraints ● Common 100kHz L1A limit stays L1 latency also same DAQ B/W likely will increase, but not necessarily by 2013 Must compress data if payload increases ECAL No changes in EB front-ends or links (EE not likely either) L1 trigger towers stay the same in EB EE could use partial sums in some clever way HCAL Use same data fibers, so speed limited to ~ 6Mb/s (guess!)

5. 2008-11-20E. Hazen5 ECAL TriDAS Review

6. 2008-11-20E. Hazen6 HCAL TriDAS Review HT R DCC TTC f HCAL HT R RCT DAQ Data @ 40MHz Trigger Primitives @ 40MHz L1A, Clk DAQ Data @ L1A DAQ DCC Events @ L1A TTC L1A, Clk HP D Q IE GOLGOL 3 Towers per GOL On Detector US C

7. 2008-11-20E. Hazen7 Calorimeter Off-Detector Links 18 Crates 9U VME ~6000 Trigger Links ~3000 Data Links ECAL (Barrel+EC) 36 S- Link ~425 SLBs 16 Crates 9U VME ~3000 Data Links HCA L 32 S- Link ~540 SLBs 1.2Gb/s 800Mb/s

8. 2008-11-20E. Hazen8 ECAL/HCAL processing (Current system) L1 Path (TPG) L2 PathDR L1 A SLB RCT Raw FE Data @ 40Mhz DR L1 A Raw FE Data @ 40Mhz T- Sum L1 Path (TPG) HTR DC C TCC VME DAQ Local L2 Path DCC SRP SL B RCT SLin k DAQ Global SLin k DAQ Global On Detector x20 0 x3 2 x9 0 x5 4 HCA L ECA L

9. 2008-11-20E. Hazen9 Upgrade Options ECAL Alone New DCC New TCC or optical SLB Modify SRP algorithms HCAL Alone New HTR+DCC system with SR capability ECAL+HCAL together (my ”Scenario I”) New ”CTR” (Calo Trigger Readout) card Receive ECAL trigger, data and HCAL data Generate TPs, possibly perform some RCT processing Perform selective readout processing on board New ”DTC” (Daq / Timing Card) Distribute timing/control signals to CTRs Harvest DAQ data using SR flags

10. 2008-09-17E. Hazen10 Selective Readout Review of existing ECAL SR Implementation options

11. 2008-09-17E. Hazen11

12. 2008-09-17E. Hazen12

13. 2008-09-17E. Hazen13

14. 2008-09-17E. Hazen14 ECAL Selective Readout Processor

15. 2008-11-20E. Hazen15 Upgrade Scenario I CTR Modules DTC Module ECAL Data ECAL Trig HCAL Data ECAL Control CCS or Similar to Trigger to DAQ Selective Readout Flags to neighbors TTC or equiv TPs L1A, Clk, Ctrl TT Flags SR Mask DAQ Data

16. 2008-11-20E. Hazen16 L2 Path Upgrade Scenario I CTR Module Details HCAL FE Data 3 TT per fiber (6-12 FE channels) DR L1 A T- Sum Tx CT ECAL FE L1 Path (TPG) DR L1 A Tx DAQ Opt Rx ~4Gb Opt Rx 800M Opt Rx 800M Selective Readout Thresholds Barrel: 1 fiber/TP Endcap: 5 fiber/TP DT C TT Flags (threshold results) to DTC Readout mask from DTC

17. 2008-11-20E. Hazen17 Cable/Fiber Counting for CTR boards Barrel -- 25 crystals = 1 TT HCAL1 fiber EB6 fibers TP Out1 fiber Total8 fibers 2448 TTs total BoardsCrates uTCA board - 12 TTs~200 ~16 ATCA/VME - 16-25 TTs100- 15010-14 Endcap -- 25 crystals = 1 RU HCAL1 fiber EB18 fibers TP Out1 fiber Total20 fibers 624 RUs total BoardsCrates uTCA board - 1 RU624 52 ATCA/VME - 6-10 RUs60-1005-10 32 Fiber s uTCA ATCA or VME 128- 200 Fibers

18. 2008-11-20E. Hazen18 DAQ Path Currently 512 FEDs possible (in theory) Each receives 100kHz * 2kB = 200MB/sec Upgrade plans (no details yet) Same 100kHz max L1A rate ”Significant” additional bandwidth capability Use commercial standards for networking Common readout path for global and local DAQ If possible embed TTC/TTS/control path in same links To accommodate 10x more bandwidth, we would need 2GB/sec per FED: Two 10GbE links in parallel per FED? Single 40GbE or other link per FED?

19. 2008-11-20E. Hazen19 DAQ Path Upgrades Hard to plan without more DAQ group input, but here is a start: ~ 10x current throughput internally Build in support for full calo selective readout Provisions for local / global DAQ via same link Commercial standard (i.e. 10GbE), perhaps on daughterboard Adapter to support current S-Link Provisions for TTC-like control on network link as well as current TTC