1. AJAI IYER COSMIC RAY LABORATORY(OOTY) DEPARTMENT OF HIGH ENERGY PHYSICS

2. Salient features of High Performance TDC(HPTDC). Design aspects of HPTDC. PCB design criteria and layout for HPTDC board. Performance testing of HPTDC board Next version of PCB DAQ results 2 Ajai Iyer,GRAPES-3,Ooty

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4. Time difference = d*sin(θ)/c where d is distance between detectors, θ is incidence angle and c is speed of light. Using Time to Digital convertors the time difference can be found which allows us to calculate the incidence angle of the shower. D1D2 d = 8 m θ0θ0 θ0θ0 D1D2 d = 8 m 4 Ajai Iyer,GRAPES-3,Ooty

5. The Time to Digital Converter (TDC 32 ) chip was acquired from CERN. A single chip can support 32 input channels. It is a 84 pin PLCC package. The timing resolution is dependant on the external clock provided. For 40 MHz it is 781 ps and for 60 MHz, 520 ps. Uses TTL standards for input and output. Can operate in start-stop or trigger mode. Parameters are programmable via JTAG using 127 setup bits and 32 control bits. 5 Ajai Iyer,GRAPES-3,Ooty

6. The High Performance TDC(HPTDC) chip was acquired from CERN. State of the art chip on 0.25 um CMOS technology. A single chip supports 32 input channels. pBGA 225 pin package. Ability to use external 40 MHz clock and internally generate clocks of 80, 160 or 320 MHz. Maximum timing resolution 24 ps. Uses LVTTL standard for input and output. Works exclusively in trigger mode only. Parameters programmable via JTAG using 647 setup bits and 40 control bits. 6 Ajai Iyer,GRAPES-3,Ooty

7. Readout32 bits/Channel. Resolution40MHz(781 ps), 160MHz(195 ps), 320MHz(98 ps), extended 320MHz(24 ps). Data Size40MHz(12+5 bits), 160MHz(12+7 bits), 320MHz(12+8 bits), extended 320MHz(12+8+2 bits). Dynamic RangeHalf of coarse time count((2^12)/2 = 2048 clock cycles = ~51us). Double pulse resolution Typical 5ns, guaranteed 10ns. Max hit rateCore Logic at 40MHz then 2MHz/Channel for all 32 channels and 4MHz/Channel if 16 channels used. Power SupplyCore +2.5V(2.3 – 2.7 V), I/O +3.3V(3.0 – 3.6 V). Input standardLVTTL/LVDS Readout standardLVTTL(Parallel), LVTTL/LVDS(serial). DNL+/-0.2 bin(781 ps),+/-0.3 bin(195 ps),+0.6/-0.25 bin(98 ps), +1.3/-0.7 bin(24 ps). INL+/-0.2 5 bin(781 ps),+/-0.5 bin(195 ps),+0.6/-1.4 bin(98 ps), +3.5/-5.0 bin(24 ps). 7 Ajai Iyer,GRAPES-3,Ooty

8. Delay by Cable or delay unit 8 TDC CLK X MHz STOP 1 STOP 2. STOP n START Delay by Cable or delay unit t = 0 LOGIC Commonly used mode in TDC is the start/stop mode. Ajai Iyer,GRAPES-3,Ooty

9. The HPTDC operates in pure trigger mode. This can be explained by the timing diagram below. 9 TDC CLK 40 MHz TRIGGER STOP 1 STOP 2. STOP n Programmable Reject limit Programmable Trigger Latency Programmable Search Window Programmable Match Window t = 0 Pseudo start point LOGIC Ajai Iyer,GRAPES-3,Ooty

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11. HPTDC only accepts LVTTL standard inputs. Suitable convertor necessary to convert TTL to LVTTL. HPTDC output data is also LVTTL standard. Large number of control options pins provided. In many cases unsure of status of pin, if left open. To reduce usage of board space control circuitry was put in a Lattice ispLSI 1016 programmable chip. Critical circuit portions have hardware redundancy. 11 Ajai Iyer,GRAPES-3,Ooty

12. GET DATA ENABLE OF O/P LATCHS O/P LATCH SIGNAL TRIGGER 12

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16. The HPTDC chip being a BGA package was only surface mount and could not be fanned out on single layer or two layer PCB with power and ground so we went for a four layer PCB with two power planes and two routing layers. The power plane had to support four different powers namely + 3.3V, + 2.5 V, + 5 V, - 5 V and it was a challenge to place and route. For the fan out of signals from HPTDC we had to use reduced track width and special vias which could fit in between the pads of the BGA. 16 Ajai Iyer,GRAPES-3,Ooty

17. HPTDC PCB WITHOUT CONNECTIONS -5V +3.3V +2.5V +5V GND 17 +5V +3.3V +2.5V -5V

18. HPTDC CHIP EXPANDED VIEW 18

19. 19 Ajai Iyer,GRAPES-3,Ooty

20. We started with the calibration test for which we used the offline calibration circuit for TDC’s. The calibration circuit generates a start and w.r.t to it a stop after a delay decided by the clock and PC. For our test each delay was repeated for 100 counts. Since the delayed stop is w.r.t start the plots you see are the average of 100 readings of stop-start for any channel. 20 Ajai Iyer,GRAPES-3,Ooty

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24. The Dynamic Range is specified by coarse counts. The range is half of total coarse counts. Count Range = (2^12)/2. This works out to ~ 51 usec. Using calibration circuit this was checked. 24 Ajai Iyer,GRAPES-3,Ooty

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26. The HPTDC has multi-hit capability which means that on any given channel it supports more than one hit. To test the multi-hit capability we made a setup and analyzed and binned the data. We concluded from the data that the HPTDC has multi- hit capability per channel but no more than four hits per channel are put in output pipeline due to internal algorithm to prevent noisy channel from utilizing full capacity of output pipeline. 26 Ajai Iyer,GRAPES-3,Ooty

27. Time gap 12.25 nsTime gap 10.68 nsTime gap 10.78 ns 27 Ajai Iyer,GRAPES-3,Ooty

28. According to the HPTDC manual the double pulse resolution is 5 ns for any given channel. Following setup was used to check it. 50 Hz oscillator Delay unit 2.38 us Discriminator Delay unit 1.5 us Xilinx SPARTAN- 3 chip Generating 4 stop signals on single channel using clock frequencies from 280 MHz down to 180 MHz TRIGGER to HPTDC STOP to HPTDC TTL o/p DOUBLE PULSE RESOLUTION TEST SETUP 28

29. We found that for 280 MHz( 3.57 ns) we are missing alternate stops as the time difference between the two stops that are recognized is 7.15 ns. Similar condition occurs for other clock frequencies till at 200 MHz( 5 ns) we found that the situation is just critical with three out of four stop signals recognized but the fourth misses intermittently. Situation stabilizes for 192 MHz( 5.2 ns) and frequencies below it with all four stop signals recognized. 29 Ajai Iyer,GRAPES-3,Ooty

30. We have run tests for Differential Non Linearity(DNL) and Integral Non Linearity(INL). Differential Non-Linearity(DNL) is defined as the variation of any code from an ideal 1 LSB step. DNL(n) = (Actual(n)/Expected(n)) – 1. Integral nonlinearity (INL) is the deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line. INL is simply the integral of the DNL So if we can get the DNL then we can compute the INL. In HPTDC the base clock is 40 MHz i.e. 25 ns so the DNL pattern repeats every 25 ns. 30 Ajai Iyer,GRAPES-3,Ooty

31. We have run tests for Differential Non Linearity(DNL) and Integral Non Linearity(INL) using following setup. 50 Hz Oscillator Discriminator Delay 440 ns HPTDC 10 MHz Oscillator TRIGGER STOP TTL NIM SETUP TO CHECK DNL OF HPTDC NON CO-RELATED 31 NIM Ajai Iyer,GRAPES-3,Ooty

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33. At 98 ps 25 ns equates to 256 bins 33

34. 34 Differential Non Linearity Plot CERN Integral Non Linearity Plot CERN

35. JTAG ports rearranged for ease of use. JTAG daisy chain re-designed to work in differential mode to support multiple modules. CAMAC addressing enabled. Control circuit in ispLSI modified to make it more resistant to spikes in input signals. Control circuit modified to dump excess data after specified read cycles to prevent mixing of data. Ground coverage on copper pour changed for more noise immunity. Power supply track improved. 35 Ajai Iyer,GRAPES-3,Ooty

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37. 37 JTAG PORTS i spLSI for CAMAC CONTROL CIRCUIT MODIFIED POWER & GROUND IMPROVED

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39. 39 RESOLUTION = 1/SLOPE= 195.32ps HPTDC RESOLUTION 195ps DELAY 25ns Ajai Iyer,GRAPES-3,Ooty

40. 40 PHILILPS HOSHIN HPTDC Ajai Iyer,GRAPES-3,Ooty

41. 41 HPTDC RESOLUTION 195ps TRIGGER LATENCY SET TO 22us Ajai Iyer,GRAPES-3,Ooty

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43. 43 REFLECTION IN CABLE REFLECTION ELIMINATED 1.5us 3.2us HPTDC RESOLUTION 195ps Ajai Iyer,GRAPES-3,Ooty

44. 44 PULSE FANOUT RTTCS GENERATOR DIRECT & REFLECTED SIGNAL ADCTDC 230m DETECTOR

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46. Ajai Iyer,GRAPES-3,Ooty 46 2370ns 2371ns

47. 47 HPTDC RESOLUTION 195ps TRIGGER LATENCY 22us Ajai Iyer,GRAPES-3,Ooty

48. Mr. Jorgen Christiansen of CERN Microelectronics Group. Special plaudits to my engineering colleagues To all my GRAPES- 3 colleagues for their valuable support in my endeavors. 48 Ajai Iyer,GRAPES-3,Ooty

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50. BLOCK DIAGRAM OF CALIBRATION SETUP 50 Ajai Iyer,GRAPES-3,Ooty

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55. The parameters of the HPTDC can be programmed by using JTAG(Joint Test Action Group) protocol. 647 setup bits and 40 control bits have to be used. We used an excel sheet to get the hex words directly and for any changes we only have to make the corresponding bits 1 or 0. We also faced the problem of data hitches from the HPTDC which we solved by probing using the JTAG interface built in and JTAG commands to see status of internal registers. For this purpose we had to write a special program to send the JTAG commands to the HPTDC and read the register values. 55 Ajai Iyer,GRAPES-3,Ooty

56. Calibration setup as follows: CALIBRATION CIRCUIT CLOCK(MHz) 40 32 25 16 10 PC CONTROLING CIRCUIT START PULSE 24 STOP CHANNELS HPTDC STOP CHANNELS DATA PC TO RECORD DATA CALIBRATION TEST SETUP DELAY 2.4 us TRIGGER 56 Ajai Iyer,GRAPES-3,Ooty

57. SETUP TO TEST MULTI-HIT D1 D2 D3 D4 57 Ajai Iyer,GRAPES-3,Ooty

58. For the purpose of the test we used a Trigger Latency of 500 ns and Trigger matching of 450 ns. Timing diagram as follows: TDC CLK 40 MHz START 50 Hz Oscillator Delay 440 ns Trigger latency 500 ns Trigger Matching 450 ns TRIGGER delayed START STOP 10 MHz non co- related Oscillator TIMING DIAGRAM FOR DNL TEST 58 Ajai Iyer,GRAPES-3,Ooty

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61. Once we got good results for the calibration we went on to check the dynamic range of the HPTDC. According to the manual it is ~ 51 usec. We programmed the chip for 50 usec and used the following setup to check. CALIBRATION CIRCUIT CLOCK(MHz) 1 FOR 50 CYCLES PC CONTROLING CIRCUIT 24 STOP CHANNELS HPTDC DATA PC TO RECORD DATA STOP CHANNELS DYNAMIC RANGE TEST SETUP DELAY 2.4 us TRIGGER 61 Ajai Iyer,GRAPES-3,Ooty

62. TTLLVTTL REDUNDANCY 62 Ajai Iyer,GRAPES-3,Ooty

63. TTLLVTTL CONTROL SIGNAL PINS INPUTS OUTPUTS HPTDC DATAREADY GET DATA 63 Ajai Iyer,GRAPES-3,Ooty

64. FOR COMPARISON THE INL PLOT AS PER THE HPTDC MANUAL Bin Frequency 64 Ajai Iyer,GRAPES-3,Ooty

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66. FOR COMPARISON THE DNL PLOT AS PER THE HPTDC MANUAL Bin Frequency 66 Ajai Iyer,GRAPES-3,Ooty

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68. FOR COMPARISON THE INL PLOT AS PER THE HPTDC MANUAL Bin Frequency 68 Ajai Iyer,GRAPES-3,Ooty