1. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Intel® MIC Architecture Debugging 1 Intel Confidential – NDA presentation; presentation contains Intel confidential information presented to customers with a non-disclosure agreement. Intel, the Intel logo, Cilk, MMX, Pentium, VTune and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries

2. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Legal Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPETY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL ® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel may make changes to specifications and product descriptions at any time, without notice. All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. Intel, processors, chipsets, and desktop boards may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Sandy Bridge and other code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more information go to http://www.intel.com/performancehttp://www.intel.com/performance Intel, Core, Xeon, VTune, Cilk, Intel and Intel Sponsors of Tomorrow. and Intel Sponsors of Tomorrow. logo, and the Intel logo are trademarks of Intel Corporation in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright ©2011 Intel Corporation. Hyper-Threading Technology: Requires an Intel® HT Technology enabled system, check with your PC manufacturer. Performance will vary depending on the specific hardware and software used. Not available on all Intel® Core™ processors. For more information including details on which processors support HT Technology, visit http://www.intel.com/info/hyperthreadinghttp://www.intel.com/info/hyperthreading Intel® 64 architecture: Requires a system with a 64-bit enabled processor, chipset, BIOS and software. Performance will vary depending on the specific hardware and software you use. Consult your PC manufacturer for more information. For more information, visit http://www.intel.com/info/em64thttp://www.intel.com/info/em64t Intel® Turbo Boost Technology: Requires a system with Intel® Turbo Boost Technology capability. Consult your PC manufacturer. Performance varies depending on hardware, software and system configuration. For more information, visit http://www.intel.com/technology/turboboosthttp://www.intel.com/technology/turboboost 2 Intel Confidential – NDA Presentation

3. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Module Outline Topics Covered –Basic use of the Intel® Debugger on the Intel® MIC Architecture applications Goals: –You will be able to describe how debugging code on the Intel® MIC Architecture differs from debugging pure host code –Be able to repeat the setup step required to get the debugger to auto-attach to an Intel® MIC Architecture application. 3 Intel Confidential – NDA Presentation

4. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Debugging Heterogeneous Intel® MIC Architecture Applications: Overview Heterogeneous debugging takes place using two coupled debuggers –Host Debugger: o Launches and debugs the host application when debugging a heterogeneous application. o Via “auto-attach,” automatically launches target debugger on offload process creation. –Target Debugger: o For heterogeneous applications  Launched when compiler runtime launches coprocessor part of a heterogeneous application. o For applications that run natively on Intel® MIC Architecture 4 Intel Confidential – NDA Presentation

5. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Debugging Heterogeneous Intel® MIC Architecture Applications: Overview The debuggers run independently except for these features –Auto-attach: o The target debugger launches automatically when the compiler runtime launches the offloaded code. o Automatically attaches to the process that has been instantiated on the coprocessor. o Breakpoints set at that time in the host debugger are set in the target debugger as well. o Auto-attach is enabled by default –Run Control: o A continue command in either debugger continues both host and coprocessor parts of the offload application. o A stop command or a stopping event, like hitting a breakpoint, stops both parts of the offload application. –Breakpoints: o A breakpoint set in either debugger is sent to the other debugger as well. 5 Intel Confidential – NDA Presentation

6. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Preparing for Heterogeneous Debugging – 1 of 3 The Intel® MIC Architecture driver includes timeouts that can negatively impact debugging. So we must disable timeouts before starting a debugging session using one of two methods 1.If the driver is already loaded, use the following command as a super user: echo "0" > /proc/lrb/0/timeout 2.Before the driver is loaded, use the following command as a super user: modprobe lrb unlimited 6 Intel Confidential – NDA Presentation

7. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Preparing for Heterogeneous Debugging – 2 of 3 1.Set up the makefile Ensure debug information is generated for both host and target code. –Change the CFLAGS and LDFLAGS in the makefile to include -g and - offload-copts: -g –O0 –The related lines of the makefile might look like this: CFLAGS = -g -offload-build -offload-copts=“-g –O0 -opt-report- phase:offload” LDFLAGS = -g -offload-build –Ensure optimization is set to –O0 to spill all variables to memory (necessary to view local variables) 7 Intel Confidential – NDA Presentation

8. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Preparing for Heterogeneous Debugging – 3 of 3 2. Set up the compiler environment source /composerxe_mic/compilervars.sh intel64 3. Attach lrb_tpt It is part of the driver installation and is located at /usr/share/larrabee/debug/lrb/lrb_tpt Intel Confidential – NDA Presentation 8

9. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Some Useful Things to Know About the Debugger Run control: Breakpoints are only set in the other debugger if there is code and debug information generated for both the host and the target part of the application. For easy debugging of a threading application, run the application with ~4-8 threads. Ending a debug session: The target debugger closes automatically when the offloaded application terminates, if the “auto close” feature has been enabled. You cannot reuse the host debugger to launch a new debug session. On abruptly stopping the debugger, it is strongly recommended to close the target debugger to avoid accumulating unused instances of the target debugger. 9 Intel Confidential – NDA Presentation

10. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Debugging Only on the Host To debug only the host side, use IDB as usual and disable auto-attach. Start the debugger using the -auto-attach=off command line option or Open Executable dialog & uncheck the corresponding check box on the Auto Attach property page. 10 Intel Confidential – NDA Presentation

11. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Starting the Heterogeneous Debugger Start the host debugger: $ idb. You will see this window. 11 Intel Confidential – NDA Presentation Note: The binary to debug should to be in same directory as where you start the debugger

12. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Setting up the Application to Debug 1 of 2 Select File->Open Executable…. The Open Executable dialog opens. 12 Intel Confidential – NDA Presentation

13. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Setting up the Application to Debug 2 of 2 Click the Browse… button next to the Executable File field and browse for your application. Click on the OK button to select the executable file and close the dialog box. 13 Intel Confidential – NDA Presentation

14. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Setting up Auto Attach Activate the Auto Attach property page and click on the Browse… button next to the Debug Info field. Locate the file containing the debug information for the lrb_tpt process. –The target debugger will connect to the KNF card and automatically attach to the first lrb_tpt* process running on the card. Click OK to accept the values and load the application into the debugger 14 Intel Confidential – NDA Presentation

15. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Loading Source Files in Preparation for Setting Breakpoints 1 of 2 When the application is loaded, open the file containing the main source code by selecting File > Open Source File…. You can type the first letters of the file name into the Filter field to narrow down the list of possible matches. 15 Intel Confidential – NDA Presentation

16. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Loading Source Files in Preparation for Setting Breakpoints 2 of 2 Now the program displayed is ready to be debugged Intel Confidential – NDA Presentation 16

17. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Debugging – Setting Breakpoints on Host and Target Code 1 of 3 Host side: similar to idb Target side: – Set a breakpoint inside this function of the offloaded code by double- clicking on the blue dot to the left of the line number to be debugged. –Start the program by clicking on the Run button/click continue button if you had been debugging on the host. 17 Intel Confidential – NDA Presentation

18. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Debugging – Setting Breakpoints on Host and Target Code 2 of 3 –On reaching the offload region, execution will temporarily stop; a second (target) debugger will be launched. 18 Intel Confidential – NDA Presentation

19. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Debugging – Setting Breakpoints on Host and Target Code 3 of 3 –All breakpoints will be transferred to the target debugger from the host debugger. –When these actions have been completed, execution of the program will resume in both debuggers. –The next breakpoint will be hit in the target debugger, the host debugger will be stopped as well. 19 Intel Confidential – NDA Presentation

20. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Figuring out Which Debugger you are Using Intel Confidential – NDA Presentation 20

21. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice 21 Debugging: Breakpoints Extract from source code: Code breakpoint Data breakpoint Code breakpoint – code not yet accessible (loaded) Thread Sync. Point Thread Sync. Point – code not yet accessible (loaded) Intel Confidential – NDA Presentation

22. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice 22 Debugging: Breakpoint Dialog Code breakpoint Data breakpoint Intel Confidential – NDA Presentation

23. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Debugging –Viewing Callstack and Locals On the top menu bar, select View->Callstack. A new tab labeled Callstack will appear in the same window as the Source Files tab in the upper left part of the debugger window. 23 Intel Confidential – NDA Presentation

24. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Debugging –Viewing Callstack and Locals On the top menu bar, select View->Locals. A new window labeled Locals will open at the bottom right portion of the debugger window (Ensure the optimization flag has been set to –O0, code generated with -O2 does not allow debug access to all local variables) Click on the Run or Continue icon in either debugger window to resume execution in both debuggers. 24 Intel Confidential – NDA Presentation

25. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice 25 Debugging: Current Thread in Thread Window Intel Confidential – NDA Presentation

26. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice 26 Control Which Thread to Debug Intel Confidential – NDA Presentation In the Threads window select the thread you would like to debug. The context menu allow you to ‘freeze’ and ‘thaw’ individual threads. When you stop/hit a breakpoint all threads will be stopped. When you continue all threads will run.

27. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice 27 Thread-specific Breakpoints Intel Confidential – NDA Presentation You can define a breakpoint only valid for one (or more) thread. In the Create Break-point Dialog you have a thread filter where you can specify which thread the break point should be valid. When a breakpoint is hit the Locals window will show values from the current thread. Shows which thread is affected

28. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice 28 Debugging Optimized Code When debugging optimized code the variables which are ‘optimized away’ are displayed in grey with a value of ‘… no value for’. Intel Confidential – NDA Presentation

29. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Exiting the Target Debugger Intel Confidential – NDA Presentation 29 The target debugger stops at ret when a breakpoint is set on the host code If you have reached the end of your debugging session, both on the host and offload code, the target debugger will close automatically. Close the host debugger manually.

30. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Debugging – Known Issues Viewing locals –Build the code with –O0 optimization flag to be able to view all the local variables. –To view locals in optimized code, copy them to something like a volatile variable to make them visible Exiting from the debugger –On clicking the red stop button, it takes time to exit when in an omp parallel section. Wait for approx. 15 – 20 seconds for the Intel® MIC debugger window to grey. –Always exit the Intel® MIC debugger first and then the host debugger, else the debugger hangs. –Close all debugger windows before starting a new debug session. 30 Intel Confidential – NDA Presentation

31. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Module Summary Topics Covered Basic use of the Intel® Debugger on the Intel® MIC Architecture applications Can you: Describe how debugging code on the Intel® MIC Architecture differs from debugging pure host code? Remember how to get the debugger to auto-attach to an Intel® MIC Architecture application? 31 Intel Confidential – NDA Presentation

32. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Labs Debugging Your Code (lesson 8) Intel Confidential – NDA Presentation 32

33. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice 33 Intel Confidential – NDA Presentation

34. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Optimization Notice 34 Optimization Notice Intel ® compilers, associated libraries and associated development tools may include or utilize options that optimize for instruction sets that are available in both Intel ® and non-Intel microprocessors (for example SIMD instruction sets), but do not optimize equally for non-Intel microprocessors. In addition, certain compiler options for Intel compilers, including some that are not specific to Intel micro-architecture, are reserved for Intel microprocessors. For a detailed description of Intel compiler options, including the instruction sets and specific microprocessors they implicate, please refer to the “Intel ® Compiler User and Reference Guides” under “Compiler Options." Many library routines that are part of Intel ® compiler products are more highly optimized for Intel microprocessors than for other microprocessors. While the compilers and libraries in Intel ® compiler products offer optimizations for both Intel and Intel- compatible microprocessors, depending on the options you select, your code and other factors, you likely will get extra performance on Intel microprocessors. Intel ® compilers, associated libraries and associated development tools may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include Intel ® Streaming SIMD Extensions 2 (Intel ® SSE2), Intel ® Streaming SIMD Extensions 3 (Intel ® SSE3), and Supplemental Streaming SIMD Extensions 3 (Intel ® SSSE3) instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. While Intel believes our compilers and libraries are excellent choices to assist in obtaining the best performance on Intel ® and non-Intel microprocessors, Intel recommends that you evaluate other compilers and libraries to determine which best meet your requirements. We hope to win your business by striving to offer the best performance of any compiler or library; please let us know if you find we do not. Notice revision #20101101 Intel Confidential – NDA Presentation

35. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice Backup Intel Confidential – NDA Presentation 35

36. Intel® Many Integrated Core Architecture Software & Services Group, Developer Relations Division Copyright© 2011, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Optimization Notice Optimization Notice 36 Some Hints …. The debugger has a powerful command language and the ability to ‘record’ a debugging session. This ‘recording’ can later be replayed hence you can generate repetitive test scenarios. You need to specify a file – specifically for I/O recording this can be quite big. Only log the commands given to the debugger Will log both command to the debugger and any output generated Intel Confidential – NDA Presentation