1. 1 Teaching Innovation - Entrepreneurial - Global The Centre for Technology enabled Teaching & Learning, N Y S S, India DTEL DTEL (Department for Technology Enhanced Learning)

2. DEPARTMENT OF INFORMATION TECHNOLOGY IV-SEMESTER COMPUTER ARCHITECTURE AND ORGANIZATION 2

3. UNIT 6:- SYLLABUSDTEL I/O Devices 1 DMA 2 Interrupt handling 3 online storage 4 3 File services 5

4. UNIT 6:- SYLLABUSDTEL Families of microprocessors Chips 6 Introduction to RISC & CISC Processors 7 Introduction to Pipelining. 8 4

5. UNIT-6 SPECIFIC OBJECTIVE / COURSE OUTCOMEDTEL Understand Online Storage and various file Services. 3 Understand the different processor architecture 2 5 The student will be able to: Understand the concepts of I/O Devices, DMA & Interrupt 1

6. DTEL 6 LECTURE 1:- Computer Peripherals Basic I/O hardware ports, buses, devices and controllers I/O Software Interrupt Handlers, Device Driver, Device- Independent Software, User-Space I/O Software Important concepts Three ways to perform I/O operations Polling, interrupt and DMAs I/O Devices

7. DTEL 7 Devices Storage devices (disk, tapes) Transmission devices (network card, modem) Human interface devices (screen, keyboard, mouse) Specialized device (joystick) LECTURE 1:- Computer Peripherals I/O Devices

8. DTEL 8 I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter. Interface between controller and device is a very low level interface. Example: Disk controller converts the serial bit stream, coming off the drive into a block of bytes, and performs error correction. Device Controller LECTURE 1:- Computer Peripherals I/O Devices

9. DTEL 9 Disk controller implements the disk side of the protocol that does: bad error mapping, prefetching, buffering, caching Controller has registers for data and control CPU and controllers communicate via I/O instructions and registers Memory-mapped I/O I/O Controller LECTURE 1:- Computer Peripherals I/O Devices

10. DTEL 10 4 registers - status, control, data-in, data-out Status - states whether the current command is completed, byte is available, device has an error, etc Control - host determines to start a command or change the mode of a device Data-in - host reads to get input Data-out - host writes to send output Size of registers - 1 to 4 bytes LECTURE 1:- Computer Peripherals

11. DTEL 11 (a) Separate I/O and memory space (b) Memory-mapped I/O (c) Hybrid LECTURE 1:- Computer Peripherals I/O Devices

12. DTEL 12 THANK YOU LECTURE 1:- Computer Peripherals

13. DTEL 13 Polling Interrupt DMA 3 ways to Perform I/O LECTURE 2:- Computer Peripherals Interrupt Handling

14. DTEL 14 Polling - use CPU to Busy wait and watch status bits Feed data into a controller register 1 byte at a time EXPENSIVE for large transfers Not acceptable except small dedicated systems not running multiple processes Polling LECTURE 2:- Computer Peripherals Interrupt Handling

15. DTEL 15 Interrupts Connections between devices and interrupt controller actually use interrupt lines on the bus rather than dedicated wires LECTURE 2:- Computer Peripherals Interrupt Handling

16. DTEL 16 CPU hardware has the interrupt report line that the CPU senses after executing every instruction device raises an interrupt CPU catches the interrupt and saves the state (e.g., Instruction pointer) CPU dispatches the interrupt handler interrupt handler determines cause, services the device and clears the interrupt LECTURE 2:- Computer Peripherals Interrupt Handling

17. DTEL 17 Interrupt Handler At boot time, OS probes the hardware buses to determine what devices are present install corresponding interrupt handlers into the interrupt vector During I/O interrupt, controller signals that device is ready LECTURE 2:- Computer Peripherals

18. DTEL 18 THANK YOU LECTURE 2:- Computer Peripherals

19. DTEL Direct Memory Access 19 Direct memory access (DMA) Assists in exchange of data between CPU and I/O controller CPU can request data from I/O controller byte by byte – but this might be inefficient (e.g. for disk data transfer) Uses a special purpose processor, called a DMA controller LECTURE 3:- Computer Peripherals

20. DTEL DMA 20 Use disk DMA as an example CPU programs DMA controller, sets registers to specify source/destination addresses, byte count and control information (e.g., read/write) and goes on with other work DMA controller proceeds to operate the memory bus directly without help of main CPU – request from I/O controller to move data to memory Disk controller transfers data to main memory Disk controller acks transfer to DMA controller LECTURE 3:- Computer Peripherals

21. DTEL DMA 21 Operation of a DMA transfer LECTURE 3:- Computer Peripherals

22. DTEL DMA 22 Handshaking between DMA controller and the device controller Cycle stealing DMA controller takes away CPU cycles when it uses CPU memory bus, hence blocks the CPU from accessing the memory In general DMA controller improves the total system performance LECTURE 3:- Computer Peripherals

23. DTEL 23 THANK YOU LECTURE 3:- Computer Peripherals

24. DTEL RISC 24 LECTURE 4:- PROCESSORS A limited and single instruction set. A large number of general purpose registers and use and compiler technology to optimize register usage. Simple instruction pipeline. Hardwired control unit. Register operands with limited addressing modes. RISC: Reduced Instruction set Computer

25. DTEL RISC 25 LECTURE 4:- PROCESSORS A single chip processor. On chip cache and floating point processor. RISC instructions are well suited to pipelines execution Relatively few instructions Fixed length, easily decoded instruction format. RISC: Reduced Instruction set Computer

26. RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly- optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. DTEL 26 RISC LECTURE 4:- PROCESSORS

27. DTEL 27 THANK YOU LECTURE 4:- PROCESSORS

28. CISC is an acronym for Complex Instruction Set Computer and are chips that are easy to program and which make efficient use of memory. Since the earliest machines were programmed in assembly language and memory was slow and expensive, the CISC philosophy made sense, and was commonly implemented in such large computers as the PDP-11 and the DECsystem 10 and 20 machines. Most common microprocessor designs such as the Intel 80x86 and Motorola 68K series followed the CISC philosophy. DTEL 28 CISC LECTURE 5:- PROCESSORS Complex Instruction Set Computer

29. But recent changes in software and hardware technology have forced a re-examination of CISC and many modern CISC processors are hybrids, implementing many RISC principles. CISC was developed to make compiler development simpler. It shifts most of the burden of generating machine instructions to the processor. For example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this. DTEL 29 CISC LECTURE 5:- PROCESSORS Complex Instruction Set Computer

30. The design constraints that led to the development of CISC (small amounts of slow memory and fact that most early machines were programmed in assembly language) give CISC instructions sets some common characteristics: A 2-operand format, where instructions have a source and a destination. Register to register, register to memory, and memory to register commands. Multiple addressing modes for memory, including specialized modes for indexing through arrays DTEL 30 CISC Attributes LECTURE 5:- PROCESSORS CISC

31. Variable length instructions where the length often varies according to the addressing mode Instructions which require multiple clock cycles to execute. DTEL 31 CISC Attributes LECTURE 5:- PROCESSORS CISC Attributes

32. Most CISC hardware architectures have several characteristics in common: Complex instruction-decoding logic, driven by the need for a single instruction to support multiple addressing modes. A small number of general purpose registers. This is the direct result of having instructions which can operate directly on memory and the limited amount of chip space not dedicated to instruction decoding, execution, and microcode storage.. DTEL 32 CISC LECTURE 5:- PROCESSORS

33. Several special purpose registers. Many CTSC designs set aside special registers for the stack pointer, interrupt handling, and so on. This can simplify the hardware design somewhat, at the expense of making the instruction set more complex. A 'Condition code" register which is set as a side-effect of most instructions. This register reflects whether the result of the last operation is less than, equal to, or greater than zero and records if certain error conditions occur. DTEL 33 CISC LECTURE 5:- PROCESSORS

34. At the time of their initial development, CISC machines used available technologies to optimize computer performance. Microprogramniing is as easy as assembly language to implement, and much less expensive than hardwiring a control unit. The ease of microcoding new instructions allowed designers to make CISC machines upwardly compatible: a new computer could run the same programs as earlier computers because the new computer would contain a superset of the instructions of the earlier computers. DTEL 34 CISC LECTURE 5:- PROCESSORS

35. As each instruction became more capable, fewer instructions could be used to implement a given task. This made more efficient use of the relatively slow main memory. Because microprogram instruction sets can be written to match the constructs of high-level languages, the compiler does not have to be as complicated. DTEL 35 CISC LECTURE 5:- PROCESSORS

36. Designers soon realized that the CISC philosophy had its own problems, including: Earlier generations of a processor family generally were contained as a subset in every new version - so instruction set & chip hardware become more complex with each generation of computers. So that as many instructions as possible could be stored in memory with the least possible wasted space, individual instructions could be of almost any length - this means that different instructions will take different amounts of clock time to execute, slowing down the overall performance of the machine. DTEL 36 CISC Disadvantages LECTURE 5:- PROCESSORS CISC

37. Many specialized instructions aren't used frequently enough to justify their existence -approximately 20% of the available instructions are used in a typical program. CISC instructions typically set the condition codes as a side effect of the instruction. Not only does setting the condition codes take time, but programmers have to remember to examine the condition code bits before a subsequent instruction changes them. DTEL 37 CISC Disadvantages LECTURE 5:- PROCESSORS CISC

38. RISC Emphasis on hardwareEmphasis on software Includes multi-clock complex instructions Single-clock, reduced instruction only Memory-to-memory: "LOAD" and "STORE“ incorporated in instructions Register to register: "LOAD" and "STORE“ are independent instructions Small code sizes, high cycles per second Low cycles per second, large code sizes Transistors used for storing complex instructions Spends more transistors on memory registers DTEL 38 CISC versus RISC LECTURE 5:- PROCESSORS

39. DTEL 39 THANK YOU LECTURE 5:- PROCESSORS

40. A technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed. -A Pipeline is a series of stages, where some work is done at each stage. The work is not finished until it has passed through all stages. With pipelining, the computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can performed. DTEL 40 Pipelining LECTURE 6:- PROCESSORS

41. How Pipelines Works The pipeline is divided into segments and each segment can execute it’s operation concurrently with the other segments. Once a segment completes an operations, it passes the result to the next segment in the pipeline and fetches the next operations from the preceding segment. DTEL 41 Pipelining LECTURE 6:- PROCESSORS

42. DTEL 42 Pipelining LECTURE 6:- PROCESSORS F 4 I 4 F 1 F 2 F 3 I 1 I 2 I 3 D 1 D 2 D 3 D 4 E 1 E 2 E 3 E 4 W 1 W 2 W 3 W 4 Instruction Clock cycle1234567 Time

43. The processing of an instruction need not be divided into only two steps. For example, a pipeline processor may process each instruction in four steps, as follows: F Fetch: read the instruction from the memory D Decode: decode the instruction and fetch the source operands. E Execute: perform the operation specified by instruction. W Write: store the result in destination location. DTEL 43 Pipelining LECTURE 6:- PROCESSORS

44. Instructions Fetch The instruction Fetch (F) stage is responsible for obtaining the requested instruction from memory. The instruction and the program counter (which is incremented to the next instruction) are stored in the IF/ID pipeline register as temporary storage so that may be used in the next stage at the start of the next clock cycle. DTEL 44 Pipelining LECTURE 6:- PROCESSORS

45. Instruction Decode The Instruction Decode (D) stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor. The instruction is sent to the control unit where it is decoded and the registers are fetched from the register file. DTEL 45 Pipelining LECTURE 6:- PROCESSORS

46. Execution The Execution (E) stage is where any calculations are performed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities. DTEL 46 Pipelining LECTURE 6:- PROCESSORS

47. Write Back The Write Back (W) stage is responsible for writing the result of a calculation, memory access or input into the register file. DTEL 47 Pipelining LECTURE 6:- PROCESSORS

48. F 1 E 1 F 2 E 2 F 3 E 3 I 1 I 2 I 3 (a) Sequential execution Instruction fetch unit Execution unit Interstage buffer B1 (b) Hardware organization Time F 1 E 1 F 2 E 2 F 3 E 3 I 1 I 2 I 3 Instruction (c) Pipelined execution Figure : Basic idea of instruction pipelining. Clock cycle1234 T ime Fetch + ExecutionDTEL 48 LECTURE 6:- PROCESSORS Pipelining

49. DTEL 49 THANK YOU LECTURE 6:- PROCESSORS

50. Fetch + Decode + Execution + Write DTEL 50 Pipelining LECTURE 7:- PROCESSORS Figure: A 4-stage pipeline. (a) Instruction execution divided into four steps F : Fetch instruction D : Decode instruction and fetch operands E: Execute operation W : Write results Interstage buffers (b) Hardware organization B1B2B3 F 4 I 4 F 1 F 2 F 3 I 1 I 2 I 3 D 1 D 2 D 3 D 4 E 1 E 2 E 3 E 4 W 1 W 2 W 3 W 4 Instruction Clock cycle1234567 Time

51. Again, pipelining does not result in individual instructions being executed faster; rather, it is the throughput that increases. Throughput is measured by the rate at which instruction execution is completed. Pipeline stall causes degradation in pipeline performance. We need to identify all hazards that may cause the pipeline to stall and to find ways to minimize their impact. DTEL 51 Pipelining LECTURE 7:- PROCESSORS

52. Advantages/Disadvantages Advantages: More efficient use of processor Quicker time of execution of large number of instructions Disadvantages: Pipelining involves adding hardware to the chip Inability to continuously run the pipeline at full speed because of pipeline hazard which disrupt the smooth execution of the pipeline. DTEL 52 Pipelining LECTURE 7:- PROCESSORS

53. Pipeline Hazards Data Hazards – an instruction uses the result of the previous instruction. A hazard occurs exactly when an instruction tries to read a register in its ID stage that an earlier instruction intends to write in its WB stage. Control Hazards – the location of an instruction depends on previous instruction Structural Hazards – two instructions need to access the same resource DTEL 53 Pipelining LECTURE 7:- PROCESSORS

54. DTEL 54 THANK YOU LECTURE 7:- PROCESSORS

55. DTEL References Books: 1.M Mano,“Computer System and Architecture”, PHI, 1993. 2.W. Stallings, “Computer Organization & Architecture”, PHI, 2001. 55 REFERENCES Textbooks: 1.V.C.Hamacher, Z.G.Vranesic and S.G.Zaky, Computer Organization, McGraw Hill, 5 th ed, 2002 2.Computer Organization, Design and Architecture (IV Ed), Sajjan G. Shiva, CRC Press 3.Computer Architecture & Organization, III Ed- J.P. Hayes.