1. GBT-FPGA Tutorial Introduction 27/06/2016GBT-FPGA Tutorial – 27/06/20161

2. Schedule 11:00 – 12:30: Introduction to the GBT-FPGA General overview GBT-FPGA structure How to importing the GBT-FPGA into your project ? 13:25 – 15:00: How to use the GBT-FPGA IP in standard mode Demo setup (Arria 10 based) How to create a reference design from scratch ? How to debug the design ? 15:20 – 16:20: How to use the GBT-FPGA IP in latency-optimized mode How to improve the design to use the latency-optimized mode ? How to debug the design ? 16:20 – 17:00: How to use an existing reference design (KC705) 17:00 – 18:00: Tips and tricks 27/06/2016GBT-FPGA Tutorial – 27/06/20162

3. GBT-FPGA Tutorial Overview: code structure 27/06/2016GBT-FPGA Tutorial – 27/06/20163

4. Outline General overview SVN Repository architecture Import the GBT-FPGA IP into my project 27/06/2016GBT-FPGA Tutorial – 27/06/20164

5. General overview What is the GBT-FPGA ? Project initiated in 2009 Library to emulate a GBT serdes in an FPGA (e-links not handled) Targets FPGA from Altera and Xilinx Supported by EP-ESE-BE section at CERN 27/06/2016GBT-FPGA Tutorial – 27/06/20165

6. GBTx 27/06/2016GBT-FPGA Tutorial – 27/06/20166

7. GBTx serial streams Downstream: GBT frames Scrambler Reed Solomon encoder Interleaver HEADER 3..0 IC 1..0 DATA 79..0 EC 1..0 FEC 31..0 Upstream: GBT frames… … or Widebus frames HEADER 3..0 IC 1..0 DATA 79..0 EC 1..0 FEC 31..0 HEADER 3..0 IC 1..0 DATA 111..0 EC 1..0 27/06/2016GBT-FPGA Tutorial – 27/06/20167

8. GBT Frame 4 60 H SC D FRM 80 21 4 Scrambler 44 60 120 RS Encoder Interleaving “randomization” of the data to ensure a good balance of the signal Ad-hoc encoding scheme allowing the correction of 2 symbols of 4 bits per encoder Adding the interleaving allows having up to 16 consecutive bit errors to be decoded 27/06/2016GBT-FPGA Tutorial – 27/06/20168

9. GBT Frame The frame is shifted out MSB first, that is: FRM, FRM, … FRM (The header shifts out first) 27/06/2016GBT-FPGA Tutorial – 27/06/20169

10. GBT Frame construction vs elink modes HEADER 3..0 IC 1..0 Elin k39 Bits 1..0 EC 1..0 FEC 31..0 Elin k38 Bits 1..0 Elin k37 Bits 1..0 Elink 32 Bits 1..0 Group 4 Group 0 HEADER 3..0 IC 1..0 Elink38 Bits 3..0 EC 1..0 FEC 31..0 Elink36 Bits 3..0 Elink34 Bits 3..0 Elink32 Bits 3..0 Elink3 Bits 3..0 Elink2 Bits 3..0 Elink1 Bits 3..0 Elink0 Bits 3..0 Group 4 Group 0 x2 x4 x8 HEADER 3..0 IC 1..0 EC 1..0 FEC 31..0 Elink36 Bits 7..0 Elink32 Bits 7..0 Group 4 Group 0 Elin k36 Bits 1..0 Elin k35 Bits 1..0 Elin k34 Bits 1..0 Elin k33 Bits 1..0 Elink4 Bits 7..0 Elink0 Bits 7..0 Elin k7 Bits 1..0 Elin k6 Bits 1..0 Elin k5 Bits 1..0 Elink 0 Bits 1..0 Elin k4 Bits 1..0 Elin k3 Bits 1..0 Elin k2 Bits 1..0 Elin k1 Bits 1..0 27/06/2016GBT-FPGA Tutorial – 27/06/201610

11. Downstream Elink mode «x2» (80Mb/s) HEADER 3..0 IC 1..0 DATA 79..0 EC 1..0 FEC 31..0 GBTx 40 «elinks» packets of 2 bits on each 80bits frame @ 40MHz + 1 Slow Control link 40 + 1 serial links @ 80Mbps Dio[0] Dout[38] Dout[39] SC eport GBTx Serdes 27/06/2016GBT-FPGA Tutorial – 27/06/201611

12. Downstream Elink mode «x4» (160Mb/s) 27/06/2016GBT-FPGA Tutorial – 27/06/201612 HEADER 3..0 IC 1..0 DATA 79..0 EC 1..0 FEC 31..0 GBTx 20 «elinks» packets of 4 bits on each 120bits frame @ 40MHz + 1 slow control link 20 serial links @ 160Mbps Dio[0] Dio[1] … Dout[37] Dout[38] Dout[39] SC eport GBTx Serdes

13. Downstream Elink mode «x4» (320Mb/s) 27/06/2016GBT-FPGA Tutorial – 27/06/201613 HEADER 3..0 IC 1..0 DATA 79..0 EC 1..0 FEC 31..0 GBTx 10 «elinks» packets of 8 bits on each 120bits frame @ 40MHz + 1 slow control link 10 serial links @ 320Mbps Dio[0] …. Dout[35] Dout[36] Dout[37] Dout[38] Dout[39] SC eport GBTx Serdes

14. General overview 27/06/2016GBT-FPGA Tutorial – 27/06/201614

15. General overview What is the GBT-FPGA ? TX_FRAMECLK 40MHz 240MHz or 120MHz Tx PLL 240MHz or 120MHz REFCLK TX_USRCLK Encoder GBT-Frame Wide-Bus TX_ISDATA_SEL Scrambler WB_EXTRADATA 32bit 84bit GBT_DATA 120bit Gearbox (Register) 20 or 40 bit PISO Serial clock Transmitter TX Link n GBT BANK RX_FRAMECLK 40MHz RX_USRCLK Encoder GBT-Frame Wide-Bus RX_ISDATA_FLAG Descrambler WB_EXTRADATA 32bit 84bit GBT_DATA 120bit Gearbox (Register) RX Link n 120bit Barrel shifter Pattern search BitSlip control RX Frameclk gen. 240MHz or 120MHz 20 or 40 bit CDR SIPO Barrel Shifter RXRECCLK Phase Algnr / Receiver 27/06/2016GBT-FPGA Tutorial – 27/06/201615

16. General overview What encoding are supported ? GBT: based on Reed-Salomon User data: 84bit Can correct up to 4 consecutive symbols (4bit) WideBus: User data: 112bit No Forward Error Correction (FEC) What are the mode supported ? Standard mode Latency: Non fixed, non deterministic and “high” Easier to implement Latency-optimized mode: Latency: Fixed, deterministic and low Complex to implement GBT Frame WideBus Frame 27/06/2016GBT-FPGA Tutorial – 27/06/201616

17. General overview What are the FPGAs characteristics? FPGA ModeEncoding ManufacturerDeviceStandardLat-optimizedGBTWideBus AlteraCyclone VYesNoTx/Rx Stratix VYes Tx/Rx Arria VYes Tx/Rx Arria 10Yes Tx/Rx XilinxVirtex 6Yes Tx/Rx Virtex 7Yes Tx/Rx Kintex 7Yes Tx/Rx Kintex UltrascaleYes Tx/Rx 27/06/2016GBT-FPGA Tutorial – 27/06/201617

18. SVN Repository architecture How to get the latest version of the GBT-FPGA IP ? SVN: https://svn.cern.ch/reps/ph-ese/be/gbt_fpga/tags/ Latest tag: GBT_FPGA_4_0_0 Foreseen: GBT_FPGA_4_0_1 (July 2016) Major bug fix: gbt_rx_decoder_gbtframe_chnsrch and gbt_rx_framealigner_pattsearch instances Are there any additional implementation ? YES, different branches SVN: https://svn.cern.ch/reps/ph-ese/be/gbt_fpga/branch/ E.g: GBT_FPGA_4_0_0_KC705_240MHZ Recommended tool: Tortoise SVN 27/06/2016GBT-FPGA Tutorial – 27/06/201618

19. DEMO 27/06/2016GBT-FPGA Tutorial – 27/06/201619

20. SVN Repository architecture altera_a10 altera_cv altera_sv xilinx_k7v7 xilinx_v6 core_sources altera_a10 altera_cv altera_sv xilinx_k7v7 xilinx_v6 core_sources example design gbt_bank tcl GBT_FPGA_4_0_0 Tag Example designs: Arria 10: PCIe40 and Altera GX development kit Cyclone V: Altera GT development kit Stratix V: AMC40 (with multi-links with Tx Lat-opt) Kintex7: FC7 and KC705 Virtex7: VC707 Virtex 6: ML605 and Glib IP Core: core_sources: encoding/decoding modules altera_* and xilinx_*: Device specific (e.g.: transceivers) TCL: TCL script to source files QSYS component description (Altera) 27/06/2016GBT-FPGA Tutorial – 27/06/201620

21. SVN Repository architecture What is the architecture of a reference design? Board specific entity Device specific entity GBT Bank Data pattern gen. Data pattern check. RX FrameClk generator Signal tap In-system sources & probes Additional modules: - Freq monitoring - PLL controller - JTAG server & GPIO - … 27/06/2016GBT-FPGA Tutorial – 27/06/201621

22. DEMO 27/06/2016GBT-FPGA Tutorial – 27/06/201622

23. SVN Repository architecture What modules are the modules included in the GBT-FPGA repository? GBT-FPGA IP: Main module of the GBT-FPGA. It contains the encoder/decoder, transceivers … Clocking modules: RX Frameclk aligner Clock divider Clock frequency measurement Data modules: GBT Data pattern generator GBT Data pattern checker Latency measurement: Data pattern matchflag Latency measurement These modules will be used and detailed during the creation of the reference design 27/06/2016GBT-FPGA Tutorial – 27/06/201623

24. DEMO 27/06/2016GBT-FPGA Tutorial – 27/06/201624

25. Import the GBT-FPGA IP into my project How to use the TCL scripts? Modification of the TCL file using an editor Import it in the project: “source mytclfile.tcl” 27/06/2016GBT-FPGA Tutorial – 27/06/201625

26. DEMO 27/06/2016GBT-FPGA Tutorial – 27/06/201626