1. Haga clic para modificar el estilo de texto del patrón Detector modules: Traditional approach and new possibilities Manuel Lozano

2. SILC Meeting2 Manuel LozanoPitch adapters, packaging, cabling: new techs.  High Energy Physics Experiments need very accurate spatial information  Particle detectors have high integration level (strips or pixels)  High number of channels per detector  Readout electronics also high integration level  Electronics has to be very close to detector  Problems with pitch adaptation between detectors and electronics Detector modules + DIFFICULT INTERCONECTION Detectors  Electronics

3. SILC Meeting3 Manuel LozanoPitch adapters, packaging, cabling: new techs. Detector modules  Traditional approach: detectors + pitch adapters + PCBs Why?

4. SILC Meeting4 Manuel LozanoPitch adapters, packaging, cabling: new techs. Printed Circuit Boards (PCBs)  Conventional PCB minimum pitch is too big compared to detectors  ATLAS-SCT strip detectors: 80 µm pitch  Up to 16 layers Class3456 Outer layer pitch (µm)600400300250 Inner layer pitch (µm)500300250200

5. SILC Meeting5 Manuel LozanoPitch adapters, packaging, cabling: new techs. High density Printed Circuit Boards  Few companies available: CICOREL, Switzerland DYCONEX, France  Minimum pitch is approaching 60 - 80 µm.  Up to 8 layers maximum Not at the minimum pitch Not enough for certain applications  Very expensive. Not suitable for large PCBs Example: Atlas SCT Forward hybrids ~ 650 €

6. SILC Meeting6 Manuel LozanoPitch adapters, packaging, cabling: new techs. Example: Cicorel  Working for ATLAS, CMS, LHC, AMS

7. SILC Meeting7 Manuel LozanoPitch adapters, packaging, cabling: new techs. Example: Dyconex

8. SILC Meeting8 Manuel LozanoPitch adapters, packaging, cabling: new techs. Pitch adapter (fanins) solution  Microelectronics technology: metal-on-glass High integration High pitch Full custom design Excellent bondability Good mechanical resistance Planarity Low mass (low atomic number) Low activation: pure material High radiation hardness ATLAS SCT forward fanin CNM

9. SILC Meeting9 Manuel LozanoPitch adapters, packaging, cabling: new techs. Pitch adapter technology ComponentMaterialThickness Glass substrate Type DESAG 263T 300  20 µm. Metal tracks Sputter deposition of: Al (99.5%) Cu (0.5%) 1  0.25 µm Passivation Positive Photoresist HiPR6512 (Arch Chemical Inc.) 2  0.25 µm M. Ullán, M. Lozano, et al. “High Pitch Metal-On-Glass Technology For Pad Pitch Adaptation Between Detectors And Readout Electronics”, IEEE Trans. on Nuclear Science, v. 51, n. 3, pp. 968-974, June 2004. CNM

10. SILC Meeting10 Manuel LozanoPitch adapters, packaging, cabling: new techs. Example: ATLAS SCT forward modules  Advantages of using fanins: ROIC chips - detectors thermal insulation  Limitations: Number of wire bonds:  Detector to detector: 768  Detector to fanins: 768  Fanins to chips: 768  Chip to PCB: 57  TOTAL: 2,361 per side  TOTAL: 4,722 per module

11. SILC Meeting11 Manuel LozanoPitch adapters, packaging, cabling: new techs. Example 2: ATLAS pixel modules  Flex PCB technology  Interconnect via Kapton foil  > 500 wire bonds per module  "3D" design  Sensor has to cover gaps in electronics

12. SILC Meeting12 Manuel LozanoPitch adapters, packaging, cabling: new techs. Chip connection  Wire bonding Only periphery of chip available for IO connections Mechanical bonding of one pin at a time (sequential) Cooling from back of chip High inductance (~1nH) Mechanical breakage risk (i.e. CMS, CDF)  Flip-chip Whole chip area available for IO connections Automatic alignment One step process (parallel) Cooling via balls (front) and back if required Thermal matching between chip and substrate required Low inductance (~0.1nH)

13. SILC Meeting13 Manuel LozanoPitch adapters, packaging, cabling: new techs. Multiple Chip Module (MCM)  Increase integration level of system (smaller size)  Decrease loading of external signals > higher performance  No packaging of individual chips  Problems with known good die: Single chip fault coverage: 95% MCM yield with 10 chips: (0.95) 10 = 60%  Problems with cooling  Still expensive  Different technologies and substrates EC Summit project demonstrator, CNM

14. SILC Meeting14 Manuel LozanoPitch adapters, packaging, cabling: new techs. MCM-D technology  Developed at CNM  Deposit additional layers on finished wafers  Up to 4 layers. Metal: Al  Dielectric: polyimide  Re-routing and under bump metallization previous to bump bonding  Passive components can also be placed

15. SILC Meeting15 Manuel LozanoPitch adapters, packaging, cabling: new techs. Advanced MCM-D technology  Developed at FhG/IZM Berlin  New MCM-D approach  Up to 5 copper layers  minimum pitch 30 µm (15 + 15)  Final metal Cu/Au  Dielectric: spin-on CBC polymer photosensitive Thickness: 2 - 6 µm  Max process temperature: 250ºC  No wire bonding

16. SILC Meeting16 Manuel LozanoPitch adapters, packaging, cabling: new techs. ATLAS pixels modules: IZM technology Images from FhG/IZM Berlin and Wüppertal University, Germany

17. SILC Meeting17 Manuel LozanoPitch adapters, packaging, cabling: new techs. ATLAS pixels modules: IZM technology Images from FhG/IZM Berlin and Wüppertal University, Germany

18. SILC Meeting18 Manuel LozanoPitch adapters, packaging, cabling: new techs. New developments in thin film circuits  Pros: Better module handling Only bump bonding, no wire bonding Reduced assembly steps Higher degree of automatization during production  Cons: Increased module size (but reduced height) More silicon consumption Lower testability High complexity of the process Industrialization: very limited number of companies available

19. SILC Meeting19 Manuel LozanoPitch adapters, packaging, cabling: new techs. Bump bonding flip chip technology  Electrical connection of chip to substrate or chip to chip face to face (flip chip)  Use of small metal bumps (bump bonding)  Process steps: Pad metal conditioning: Under Bump Metallisation (UBM) Bump growing in one or two of the elements Flip chip and alignment Reflow Optionally underfilling CNM

20. SILC Meeting20 Manuel LozanoPitch adapters, packaging, cabling: new techs. Bump bonding flip chip technology  Expensive technology Specially for small quantities (as in HEP) Big overhead of NRE costs  Minimal pitch reported: 18 µm but...  Few commercial companies for fine pitch applications (< 75 µm)  Bumping technologies Evaporation through metallic mask Evaporation with thick photoresist Screen printing Stud bumping (SBB) Electroplating Electroless plating Conductive Polymer Bumps Indium evaporation

21. SILC Meeting21 Manuel LozanoPitch adapters, packaging, cabling: new techs. Screen printing  Process steps Stencil alignment Solder paste deposition with a squeegee Reflow into spheres  Characteristics Minimum pitch: 200 µm Stencil printing thickness: 100 - 50 µm Same bump height Solder pastes:  Sn/Pb, Sn/Pb/Ag, Sn/Ag, Sn/Sb  Pb free pastes: In, Pd, Sn/Ag/Cu Most widespread Very high yield On wafers, or big chips (alignment marks) CNM

22. SILC Meeting22 Manuel LozanoPitch adapters, packaging, cabling: new techs. Electroplating bump bonding  Process steps Ni/Au sputtering over the whole wafer Photolithography to delimit bump areas (thick photoresist) Electrolytic deposition of base layer and bumps Photoresist elimination Etch wafer metalisation Reflow into spheres  Characteristics Minimum pitch 40 µm Bump height 30 - 75 µm On wafers CNM

23. SILC Meeting23 Manuel LozanoPitch adapters, packaging, cabling: new techs. Electroless plating  Process steps Pad conditioning Zinkation Bump electroless deposition  Characteristics No need for electrodes Photolithography not required Bump material: Ni/Au Minimum pitch 75 µm Bump diameter 40 µm Bump height 5 - 30 µm Indium bumps possible On wafers or chips FhG/IZM

24. SILC Meeting24 Manuel LozanoPitch adapters, packaging, cabling: new techs. Indium deposition  Process steps Bump conditioning (if necessary) Photolithography to delimit bump areas In evaporation on cooled substrates Photoresist elimination and lift-off  Characteristics Small size bump  Requires bumping both elements Low melting point: 156ºC  Not compatible with further soldering Room temperature assembly by high pressure  Possibility of substrate damage Low mechanical strength Expensive For heterogeneous systems with thermally mismatched materials AIT, Hong Kong

25. SILC Meeting25 Manuel LozanoPitch adapters, packaging, cabling: new techs. Flip chip alignment  Special equipment required for pick, align, and place  Self alignment during reflow allows certain degree of tolerance in alignment  Not true for In bumping Requires special pick and place machines with 1-2 µm accuracy, planarity control, and high applied pressure

26. SILC Meeting26 Manuel LozanoPitch adapters, packaging, cabling: new techs. Bump bonding  Sn/Pb problems with Pb, it is an alpha emitter Bad for particle detectors Anyway Pb is limited in use due to environmental issues  Alternatives to Pb Lower temp. Higher temp.  Reflow temp. > Melt. Point + 40ºC Melt. Point (ºC) 57Bi 43Sn139 62Sn 36Pb 2Ag179 63Sn 37Pb183 90Sn 9.5Bi 0.5Cu198 96.5Sn 3Ag 0.5Cu218 96.3Sn 3.7Ag221 95Sn 5Sb236 89Sn 10.5Sb 0.5Cu247 20Sn 80Au280

27. SILC Meeting27 Manuel LozanoPitch adapters, packaging, cabling: new techs. INTEL Other advances: 3D vertical integration

28. SILC Meeting28 Manuel LozanoPitch adapters, packaging, cabling: new techs. 3D technology  Potential application to tracking detectors: vector detector  Provides X, Y,  X,  Y : intersecting position + angular direction Image from E. Heijne, CERN

29. SILC Meeting29 Manuel LozanoPitch adapters, packaging, cabling: new techs. Wafer bonding and 3D stacking  Two wafers directly bonded face to face  Allow thin wafer with CMOS electronics directly on top of detectors (for instance)  Direct metal to metal bonding  Skip the bump bonding process  Needs wafer via etching, and metal filling S. Farrens, R. Pelzer, et al., EV Group, Schaerding, Austria

30. SILC Meeting30 Manuel LozanoPitch adapters, packaging, cabling: new techs. Wafer bonding and 3D stacking  Or even three wafers...  Use en particle detectors ? Tezzaron Semiconductor

31. SILC Meeting31 Manuel LozanoPitch adapters, packaging, cabling: new techs. Silicon via holes  Examples of holes made at CNM  Aspect ratio 25:1  Minimum diameter tested 10 µm

32. SILC Meeting32 Manuel LozanoPitch adapters, packaging, cabling: new techs. ALCATEL 601-E  Deep RIE-ICP.  Load-lock manual one 4” wafer  SF 6 etching. C 4 F 8 passivation  Cooled mechanical clamping: He- liquid N 2  Possibility of cryogenic etching. MaterialGas SiSF 6 + C 4 F 8 SiO 2 SF 6 Si 3 N 4 SF 6 SiCSF 6 + O 2

33. SILC Meeting33 Manuel LozanoPitch adapters, packaging, cabling: new techs. Other uses of ICP RIE: edgless detectors  Active silicon area very close to beam  Edges patterned by deep RIE  Minimum distance 25 µm G.Pellegrini, M.Lozano, et al. "Edgeless detectors fabricated by dry etching process". Nuclear Instruments and Methods. To be published

34. SILC Meeting34 Manuel LozanoPitch adapters, packaging, cabling: new techs. Strip detectors  We saw examples of pixel detectors.  The same approach can be applied to strips  Readout chips bump bonded on detectors Which has to increase the area  Wire bonding in detector, not in ROIC Minimum number of wires Can be replaced by cables, thus eliminating wire bonding  It is necessary to use low consumption techniques in ROICs to avoid heating the detectors

35. SILC Meeting35 Manuel LozanoPitch adapters, packaging, cabling: new techs. Conclusion There are many new technologies being developed that can be interesting for particle detectors in HEP We only need now clever ideas to obtain benefits from them