1. Status of ETD D. Breton, U.Marconi, S.Luitz WS summary plenary session October 1 st 2010 D. Breton - SuperB Frascati Workshop – September 2010

2. Tuesday afternoon, we held the first session, dedicated to front-end electronics We had a very good attendance There is now a quite good coherence between the different subdetector designs and the global system requirements. Most subsystems are currently designing and testing new prototype electronics Some are/will be very soon tested with particles The main evolution in the designs is the fact that the SVT very front-end will become triggered For layers 1 to 5, a new ASIC will be designed, based on FSSR2, but with an improved SNR, the capability of dealing with high background rates, and a triggered readout Layer 0 will have a dedicated ASIC, which will also be readout in a triggered manner The main consequence is that SVT cannot anymore aim at (be required to ?) participating in the level 1 trigger, except if a dedicated implementation is foreseen in the new FSSR3 => this has to be clarified as soon as possible Issues from ETD session 1 D. Breton - SuperB Frascati Workshop – September 2010

3. Some subdetectors presented new prototype electronics for tests with particles Tests of new prototypes D. Breton - SuperB Frascati Workshop – September 2010 FPID FEMC 16-channel 10-ps TDC based on Waveform Digitizers (Orsay) on SLAC CRT 5-channel Range Board (Rome) 25-crystal test beam setup (=>CERN)

4. Wednesday morning, we held the second session, dedicated to general electronics One remark: Aula Toushek is really not adequate for reduced attendance … (I actually wish we could fill it up) There were 3 presentations: Serial link Loss-of-Lock impact on system dead time Status of R&D on ROM and developments on FCTS A few ideas about grounding and shielding for SuperB We had no presentation about the control link irradiation results because said irradiations will only take place in October/November  we should get these interesting results in Caltech  I’m not sure the irradiation tests of the readout SERDES are funded yet (this is yet a crucial step for their validation) Issues from ETD session 2 D. Breton - SuperB Frascati Workshop – September 2010

5. Statistical analysis of the impact of Loss Of Lock of the Clink deserializer on data quality has been set up: This is an crucial feature for the clock and control distribution This study reveals the need for a faster feedback than currently foreseen Serial link Loss-of-Lock impact on system dead time (S.Cavaliere) D. Breton - SuperB Frascati Workshop – September 2010 Feedback path Dead time for 5ms feedback time

6. ROM R&D (D.Charlet for Bologna team) From FE Ethernet 1Gb/s Evaluation board 10Gb Ethernet board PCIExpress PC Ethernet 10Gb/s PC farm UDP Throttle switch Farm status or InfiniBand PC simply used as a bridge between the Front-End readout link and network links. Evaluation board houses a ML605 XILINX FPGA which: manages the Front End board link. performs data compression, digital filtering, buffering,... generates throttle commands toward FCTS via Ethernet using UDP protocol. Transfer rate between the two board up to 1600MByte/s. No board development. Offers a wide flexibility. The choice of the type of output link could be delayed.

7. Status of FCTS (D.Charlet) ATCA backplane could be used for FCTS crate. Custom use. One main crate for all detector ROM throttle use Ethernet link with UDP protocol. IP number used as FARM natural throttle. Farm status is mandatory. Switch fabric Clock Interface Base Interface

8. A few ideas about grounding and shielding for SuperB (D.Breton) D. Breton - SuperB Frascati Workshop – September 2010 Grounding and shielding is a key element in the success of the design.  it is usually considered as a boring item.  but spending some time thinking of it from the beginning can save you so much time and trouble eventually... Grounding mainly consists in having strong equipotential grounds for subdetectors while ensuring good and independent current return paths to the power supplies Supplies can be floating DC/DC blocks, feeding regulators located on the detector next to the front-end electronics, and cleanly referenced to ground there. Shielding concerns all cables, especially those transporting perturbative signals or those sensitive to it. In order to be effective, cable shield has to be connected at both ends.

9. Thursday afternoon, we held the third session, dedicated to first level trigger Attendance was reduced VERY few people participated in the discussion (unfortunately) For the TDR writing, we need to further study: Rates (Bhabhas, Irreducible, Backgrounds) Background suppression Trigger efficiencies & physics performance L1 accept rate ADC sampling frequencies in DCH and EMC front-end Time separation capability Between subsequent triggers. O(100ns) required if rate extrapolations are correct Intrinsic per-channel dead-time  overall trigger dead time Trigger jitter / time resolution / latency Trigger issues(1) D. Breton - SuperB Frascati Workshop – September 2010 Copyright S.Luitz

10. Based on these elements, we need ~ 2 FTE to produce a simple simulation of the charged and neutral triggers This is mostly physicist work  we’ll start discussing with Rome3 people to see if they could participate in it  otherwise we’ll have to look for postdoc candidates This may have implications on the detector design => this is becoming urgent If we can validate our baseline design, SVT could be left out of the game We really need to build a trigger group made of a mix of physicists and engineers  each subdetector has to name a trigger contact person (decided at TB)  I would ask for (a physicist + an engineer) for DCH and SVT  there are known potential external candidates (some could only be consultants) but they would only become available with prospect of approval Trigger (2) D. Breton - SuperB Frascati Workshop – September 2010 Copyright S.Luitz

11. Subsystems now have a quite stable electronics design There are however some major evolutions like a triggered SVT Most subsystems are currently designing and testing prototype electronics In some cases, there is a lack of money/manpower for the R&D in view of the TDR Work is going ahead in all the fields of the global system electronics R&D on serial links and ROM are well on tracks We should get all their results on time for the TDR Other items are well covered and enough defined for TDR writing Subdetectors have to start thinking about their grounding, powering and shielding rules Level 1 trigger is the most critical item these times => we urgently need to build the trigger group. => we have to perform simulations for the TDR => we need to find new collaborators for this area (Rome3, …) => we will organize a trigger meeting (maybe video) in November Conclusion on ETD D. Breton - SuperB Frascati Workshop – September 2010