1. CS-EE 481 Spring 2005 1March, 2005 University of Portland School of Engineering Project Bighorn CMOS Low Pass Switched Capacitor Filter Team Brien Bliatout DeMarcus Levy Sam Russum Advisor Dr. Peter Osterberg Industry Representative Mr. Mike DeSmith

2. CS-EE 481 Spring 2005 2March, 2005 University of Portland School of Engineering Overview Introduction to an LPSCF Accomplishments so far Current Issues and Concerns Plans for the future Conclusion

3. CS-EE 481 Spring 2005 3March, 2005 University of Portland School of Engineering General LPSCF Schematic

4. CS-EE 481 Spring 2005 4March, 2005 University of Portland School of Engineering Purpose of SCFs No Resistors High Accuracy Can be implemented in ICs

5. CS-EE 481 Spring 2005 5March, 2005 University of Portland School of Engineering Schematic of Project Bighorn

6. CS-EE 481 Spring 2005 6March, 2005 University of Portland School of Engineering Frequency Response

7. CS-EE 481 Spring 2005 7March, 2005 University of Portland School of Engineering Transfer Function Equation

8. CS-EE 481 Spring 2005 8March, 2005 University of Portland School of Engineering Schematic of Project Bighorn

9. CS-EE 481 Spring 2005 9March, 2005 University of Portland School of Engineering Ideal Clock Signal Outputs

10. CS-EE 481 Spring 2005 10March, 2005 University of Portland School of Engineering 555 Schematic

11. CS-EE 481 Spring 2005 11March, 2005 University of Portland School of Engineering Clock Schematic

12. CS-EE 481 Spring 2005 12March, 2005 University of Portland School of Engineering Delay Line Schematic

13. CS-EE 481 Spring 2005 13March, 2005 University of Portland School of Engineering Ideal Clock Signal Outputs

14. CS-EE 481 Spring 2005 14March, 2005 University of Portland School of Engineering Accomplishments SUCCESS! The Macro-model works.

15. CS-EE 481 Spring 2005 15March, 2005 University of Portland School of Engineering Results Deliverable to Dr. Osterberg for future EE451 class demonstrations. Ready to test MOSIS chip.

16. CS-EE 481 Spring 2005 16March, 2005 University of Portland School of Engineering Results - continued Yellow = 200mV Input, Blue = Output Spice Simulation

17. CS-EE 481 Spring 2005 17March, 2005 University of Portland School of Engineering Results - continued Yellow – Φ 1, Blue = Node 1 Spice Simulation

18. CS-EE 481 Spring 2005 18March, 2005 University of Portland School of Engineering Results - continued Yellow – Φ 1, Blue = Node 4 Spice Simulation

19. CS-EE 481 Spring 2005 19March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = Node 5 Insert Node 5 and compare to Mike’s Spice Simulation

20. CS-EE 481 Spring 2005 20March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = V out

21. CS-EE 481 Spring 2005 21March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = V out

22. CS-EE 481 Spring 2005 22March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = V out, Roll-off Frequency

23. CS-EE 481 Spring 2005 23March, 2005 University of Portland School of Engineering Results - continued Yellow – V in, Blue = V out

24. CS-EE 481 Spring 2005 24March, 2005 University of Portland School of Engineering Macro Model

25. CS-EE 481 Spring 2005 25March, 2005 University of Portland School of Engineering Layout

26. CS-EE 481 Spring 2005 26March, 2005 University of Portland School of Engineering Layout Close-up

27. CS-EE 481 Spring 2005 27March, 2005 University of Portland School of Engineering Will MOSIS Chip Work? Why it might not: –On resistance of the transistors are too high τ = RC Why it might: –It is possible that capacitors were sized incorrectly on chip making the capacitors smaller in value.

28. CS-EE 481 Spring 2005 28March, 2005 University of Portland School of Engineering Milestone Table

29. CS-EE 481 Spring 2005 29March, 2005 University of Portland School of Engineering Concerns/Issues Paper work.

30. CS-EE 481 Spring 2005 30March, 2005 University of Portland School of Engineering Plans Test MOSIS chip Prototype Release Final Report

31. CS-EE 481 Spring 2005 31March, 2005 University of Portland School of Engineering Conclusion SUCCESS! Paper work is all that’s left.