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Slide 1 SLIP 2004 Payman Zarkesh-Ha, Ken Doniger, William Loh, and Peter Bendix LSI Logic Corporation Interconnect Modeling Group February 14, 2004 Prediction.

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Presentation on theme: "Slide 1 SLIP 2004 Payman Zarkesh-Ha, Ken Doniger, William Loh, and Peter Bendix LSI Logic Corporation Interconnect Modeling Group February 14, 2004 Prediction."— Presentation transcript:

1 Slide 1 SLIP 2004 Payman Zarkesh-Ha, Ken Doniger, William Loh, and Peter Bendix LSI Logic Corporation Interconnect Modeling Group February 14, 2004 Prediction of Interconnect Adjacency Distribution: Derivation, Validation, and Applications

2 Slide 2 SLIP 2004 Outline  Motivation  Interconnect Adjacency Model  Derivation  Validation  Applications  Conclusion

3 Slide 3 SLIP 2004 Effect of Geometry on Capacitance 0.20 0.15 0.10 0.05 0.00 Line Capacitance [fF/  m] Ref. -26% -51% +80% +42%

4 Slide 4 SLIP 2004  How to choose the geometry for system level modeling of interconnect capacitance:  A real system is a mix of many cases.  A statistical approach is required to predict the capacitance distribution more realistically. Motivation  We will derive the interconnect geometry distribution that produces circuit variations.

5 Slide 5 SLIP 2004 Outline  Motivation  Interconnect Adjacency Model  Derivation  Validation  Applications  Conclusion

6 Slide 6 SLIP 2004  Wire placement in a random logic network is complex and irregular enough to be modeled by a probability distribution involving “coin flipping”.  Average channel utilization, p, is known. Assumptions

7 Slide 7 SLIP 2004 What is Adjacency? Interconnect adjacency is the fractional length of an interconnect that possesses neighbors at minimum spacing.

8 Slide 8 SLIP 2004 Routing Channel Definitions Grid Empty space Interconnect Window Victim Line

9 Slide 9 SLIP 2004 Simple Case: Unit Length System Window of size n=9 Bernoulli Distribution n = total number of grids k = number of filled grids p = probability of filling

10 Slide 10 SLIP 2004 Realistic System  Wires are random length (not all unit length).  Window size, n, is not constant anymore.  Wires may cross window boundaries. Derivation details available in the paper.

11 Slide 11 SLIP 2004  Average channel utilization, p.  Minimum and maximum segment length.  Grid size.  Segment length distribution.  Can be derived from Rent’s rule by partitioning.  Can be fit empirically. Model Input

12 Slide 12 SLIP 2004 M2 Segment Length Distribution Technology = 130nm Metal layer = M2 Min wire length = 1.0  m Max wire length = 100  m

13 Slide 13 SLIP 2004 Other Segment Length Distribution

14 Slide 14 SLIP 2004 Outline  Motivation  Interconnect Adjacency Model  Derivation  Validation  Applications  Conclusion

15 Slide 15 SLIP 2004 0% 50% 100% 150% 200% 0.20 0.15 0.10 0.05 0.00 0% 50% 100% 150% 200% 0.20 0.15 0.10 0.05 0.00 Real Data Model Comparison with Actual Data PDF Channel utilization = 40% Min wire length = 1.0  m Max wire length = 100  m Grid size = 0.01  m Metal layer = M2 Technology = 130 nm Adjacency Probability Density Function Adjacency Probability Density Function Peak @ 0%Peak @ 100% Peak @ 200% Peak @ 0%Peak @ 100% Peak @ 200%

16 Slide 16 SLIP 2004 Comparison with Actual Data CDF

17 Slide 17 SLIP 2004 Comparison with Actual Data CDF Metal layer = M4 Channel utilization = 42% Gate pitch = 1.0  m Max wire length = 150  m Grid size = 0.01  m Metal layer = M3 Channel utilization = 50% Gate pitch = 1.0  m Max wire length = 150  m Grid size = 0.01  m

18 Slide 18 SLIP 2004 Sensitivity to Length Distribution Change in  Change in l max

19 Slide 19 SLIP 2004 Adjacency Distribution Change with p

20 Slide 20 SLIP 2004 Outline  Motivation  Interconnect Adjacency Model  Derivation  Validation  Applications  Conclusion

21 Slide 21 SLIP 2004 Statistical Crosstalk Analysis

22 Slide 22 SLIP 2004 Sensitivity Analysis Adjacency = 0% Adjacency = 200%

23 Slide 23 SLIP 2004 Interconnect Statistical Reference M3 M4 M2

24 Slide 24 SLIP 2004 Outline  Motivation  Interconnect Adjacency Model  Derivation  Validation  Applications  Conclusion

25 Slide 25 SLIP 2004 Conclusions  Compact model for Interconnect Adjacency Distribution for random logic networks is derived.  The model uses only system level generic parameters such as segment length distribution and channel utilization. This enables us to predict future system level performance.  Comparison to product data confirms the accuracy of the model.  Some possible applications of the adjacency are proposed.

26 Slide 26 SLIP 2004 We acknowledge Ralph Iverson from Magma Design Automation for his generous support in the extraction of the real data. Acknowledgement


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