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Analog Integrated Circuits Lecture 1: Introduction and MOS Physics ELC 601 – Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina

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Presentation on theme: "Analog Integrated Circuits Lecture 1: Introduction and MOS Physics ELC 601 – Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina"— Presentation transcript:

1 Analog Integrated Circuits Lecture 1: Introduction and MOS Physics ELC 601 – Fall 2013 Dr. Ahmed Nader Dr. Mohamed M. Aboudina anader@ieee.org maboudina@gmail.com Department of Electronics and Communications Engineering Faculty of Engineering – Cairo University

2 10/2/2016© Ahmed Nader, 2013 2 MOS: Subthreshold (Weak Inversion) Subthreshold Conduction: For V GS near V TH, I D has an exponential dependence on V GS : Max transconductance efficiency Used for low currents & low frequency applications

3 10/2/2016© Ahmed Nader, 2013 3 MOS: Intrinsic Capacitance C1 is the gate-channel capacitance C2 is the channel-bulk depletion capacitance C3 & C4 is the overlap gate-source(drain) capacitance C5 & C6 is the source/drain –bulk junction capacitance (bottom- plate and sidewall) Note that junction capacitors are voltage-dependent (non-linear)

4 10/2/2016© Ahmed Nader, 2013 4 MOS: Intrinsic Capacitance

5 10/2/2016© Ahmed Nader, 2013 5 MOS Device as a Capacitor: Varactor Assignment 1a: There is a special device with n-doping in an NWELL. Plot the characteristics of such a device. Comment on its properties.

6 10/2/2016© Ahmed Nader, 2013 6 Small Signal Model The slope of the diode characteristic at the Q-point is called the diode conductance and is given by: g d is small but non-zero for I D = 0 because slope of diode equation is nonzero at the origin. Diode resistance is given by:

7 10/2/2016© Ahmed Nader, 2013 7 Small Signal Operation of a Diode Subtracting I D from both sides of the equation, For i d to be a linear function of signal voltage v d, This represents the requirement for small-signal operation of the diode.

8 10/2/2016© Ahmed Nader, 2013 8 Current Controlled Attenuator Magnitude of ac voltage v o developed across diode can be controlled by value of dc bias current applied to diode. From dc equivalent circuit I D = I, From ac equivalent circuit, For R I = 1 k , I S = 10 -15 A, If I = 0, v o = v i, magnitude of v i is limited to only 5 mV. If I = 100  A, input signal is attenuated by a factor of 5, and v i can have a magnitude of 25 mV.

9 10/2/2016 9 Small-Signal Model of a MOS (Two-Port Model) Using 2-port y-parameter network, The port variables can represent either time-varying part of total voltages and currents or small changes in them away from Q-point values.

10 10/2/2016 10 Small-Signal Model of a MOS Since gate is insulated from channel by gate-oxide input resistance of transistor is infinite. Small-signal parameters are controlled by the Q-point. For same operating point, MOSFET has lower transconductance and lower output resistance that BJT. Transconductance: Output resistance:

11 MOS Transistor © Ahmed Nader, 2013 11 10/2/2016 Important Trade-Offs!! Gain Vs. Current Gain Vs. Speed Gain Vs. Voltage Swing

12 MOS Transistor © Ahmed Nader, 2013 12 Small Signal Model: Body Effect 10/2/2016 Drain current depends on threshold voltage which in turn depends on v SB. Back-gate transconductance is: 0 <  < 1 is called back-gate tranconductance parameter.

13 10/2/2016© Ahmed Nader, 2013 13 Small-Signal Model of a MOS: High Frequency Model Voltage dependent current source (g m V gs ) models dependence of drain current on gate-source voltage Output resistance models dependence of drain current on drain- source voltage (channel length modulation) Voltage dependent current source (g mb V bs ) models dependence of drain current on bulk-source voltage (body effect)

14 MOS Transistor © Ahmed Nader, 2013 14 Useful Model Small Signal: + - 10/2/2016

15 MOS Transistor © Ahmed Nader, 2013 15 Special Cases Bias point 10/2/2016

16 © Ahmed Nader, 2013 16 Deep Sub-Micron Technologies

17 10/2/2016© Ahmed Nader, 2013 17 Analog Low-voltage – High- Speed trade-off Fixed for the technology and fixed L

18 10/2/2016© Ahmed Nader, 2013 18 Deep Sub-Micron Technologies Some small geometry effects: 1- Gate leakage 2- Threshold voltage variation 3- Output impedance variation with V DS (non-linearity ) 4- Mobility degradation with vertical field 5- Velocity saturation 6- Reliability Effects (GO, Hot Carrier, NBTI,..) 7- Stress Effects (STI, Well Proximity,..) Assignment 1b: Choose one of those effects in 6 or 7 and describe it in details (physical meaning, effect on performance, etc.)

19 10/2/2016 19 Deep Sub-Micron Technologies © Ahmed Nader, 2013 What about scaling of V th ?

20 10/2/2016© Ahmed Nader, 2013 20 Deep Sub-Micron Technologies – Mobility degradation with Vertical Field Carriers are confined to a narrower region below oxide- silicon interface leading to more carrier scattering and hence lower mobility Assignment 1c: Find an expression for HD3

21 10/2/2016© Ahmed Nader, 2013 21 Deep Sub-Micron Technologies – Velocity Saturation

22 10/2/2016© Ahmed Nader, 2013 22 Deep Sub-Micron Technologies – Velocity Saturation

23 10/2/2016© Ahmed Nader, 2013 23 MOS Device Models Level 3 Model BSIM (Berkeley Short-Channel IGFET Model)

24 10/2/2016© Ahmed Nader, 2013 24 MOS Device Models

25 10/2/2016© Ahmed Nader, 2013 25 Analog Layout

26 10/2/2016© Ahmed Nader, 2013 26 Analog Layout

27 10/2/2016© Ahmed Nader, 2013 27 Analog Layout

28 10/2/2016© Ahmed Nader, 2013 28 Analog Layout Adding Dummies. How can dummies help in STI? Connect gate (poly) from both sides

29 10/2/2016© Ahmed Nader, 2013 29 Analog Layout: Inter-digitation

30 10/2/2016© Ahmed Nader, 2013 30 Analog Layout

31 10/2/2016© Ahmed Nader, 2013 31 Analog Layout: Common Centroid

32 10/2/2016© Ahmed Nader, 2013 32 Analog Layout

33 10/2/2016© Ahmed Nader, 2013 33 Resistor Layout

34 10/2/2016© Ahmed Nader, 2013 34 Capacitor Layout

35 10/2/2016© Ahmed Nader, 2013 35 Inductor Layout

36 10/2/2016© Ahmed Nader, 2013 36 Inductor Layout Spiral Inductor Calculator (Stanford): http://www-smirc.stanford.edu/spiralCalc.htmlhttp://www-smirc.stanford.edu/spiralCalc.html Assignment1: Using ASITIC tool: http://rfic.eecs.berkeley.edu/~niknejad/doc-05-26-02/asitic.htmlhttp://rfic.eecs.berkeley.edu/~niknejad/doc-05-26-02/asitic.html Design an Inductor with L=2nH and Q>10

37 10/2/2016© Ahmed Nader, 2013 37 Analog Layout: Summary

38 10/2/2016© Ahmed Nader, 2013 38 Analog Layout: Example

39 10/2/2016© Ahmed Nader, 2013 39 Analog Layout: Example

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