1. HO / RPC Trigger Links Optical SLB Review E. Hazen, J. Rohlf, S.X. Wu Boston University

2. OSLB Specifications for HCAL HO -> RPC muon trigger ● Send 32 bits each BX using GOL at 1.6Gbaud: – 24 bits data – 3 bits BCn, BC0 – 4 bits error-check code ● One 3-output SLB per HTR ● Provide bunch occupancy histogram for synchronization checking ● HTR local bus upgrade of firmware ● BIST features (send fixed/random test pattern)

3. OSLB Status ● Status: – PCB Design Complete – Preliminary firmware essentially done – Request for Quote out on all parts ● Plans: – Fabricate 2 prototypes by end March – Test at BU using HTR optical receiver – Test at CERN in May/June ● Documents posted: – http://joule.bu.edu/~hazen/cms_trig/

4. HCAL (HO) in RPC Trigger TRIGGER BOARD READOUT BOARD SPLITTER S-link to DAQ to Level-1 trigger 90 m @ 1.6Gbit/s up to 5 m LVDS @ 80MHz QI E GO L QI E HTR (Readout) Board Optical Tx HCAL Front-end New 'Optical SLB' Transmitter mezzanine board

5. Latency Estimate According to the (next) slide from RPC group, our input is due at tick 46, so it is tight! (They say that a couple of clocks later is OK)

7. Rohlf mapping of 11/29/05 ●  36 bits / SLB ● No HTR-HTR interconnects ● 4 different mappings ● 2 or 3 links per HTR

8. Spartan-3 FPGA GOL v1.0 Finisar SFF Trans. HTR Connectors (3 x PMC) Power TP Data (72) TTC B'Cst (6) TTC BC STB TTC CLK TTC BCR Local Bus Data (16) Local Bus Adx (7) Local Bus CSn Local Bus R/W TTC Fanout Clock (PECL) Fanout BC0 (PECL) Clock Distribution Clocks (3) Generic Flash Memory JTAG GOL v1.0 Finisar SFF Trans. GOL v1.0 Finisar SFF Trans. Link signals (36) I2C Bus XC9572 CPLD local bus FPGA config JTAG from HTR used to configure CPLD and for debugging Firmware can be updated through local bus (CPLD controls flash)

9. Clock Scheme QPLL RX_CLK from HTR Philips PCK2111 low-skew LVDS clock fanout (selectable input) FPGA GOL NB4N527S Dual “AnyLevel” to LVDS Rx/Driver Clock Data

10. SFF Optical Transceiver GO L SFF Optical Transceiver GO L SFF Optical Transceiver GO L PLL, FPGA Flash etc

11. Optical Receiver Optical Receiver Optical Receiver 1.2V LDO Regulator xc3s400 fpga XC9572 CPLD 2Mbit Flash GO L QPL L Cloc k Fano ut 2.5V LDO Regulato r Top layer (blue) Top solder mask Top silkscreen View from side facing HTR

12. Bottom layer (red) Bottom solder mask Bottom silkscreen

13. Layer 2 GROUND

14. Layer 3 2.5V Inductor (EMI reduction)

15. Layer 4 Signal

16. Layer 5 signal

17. Layer 6 3.3V, 1.2V 1.2V area

18. Layer 7 GROUND

19. Fabrication Notes 0.005 0.012 Layer 1 (signal) Layer 2 (GND) Layer 3 (2.5V) Layer 4 (signal) Layer 5 (signal) Layer 6 (3.3V/1.2V) Layer 7 (GND) Layer 8 (signal) Board Stackup Total thickness ~.060 ½ +1 oz 0.002 ½ oz 0.0007 ½ +1 oz 0.002 Z 0 ≈ 60  for all

20. Firmware Notes ● Two programmable devices (CPLD and FPGA) ● CPLD (XC9572) – Programmed via JTAG; rarely changed – Controls configuration of FPGA and local bus access ● FPGA (Xilinx Spartan-3) – Configured either via local bus at any time or; from flash memory at power-up – Flash memory can be programmed via local bus allowing on-line firmware updates

21. FPGA firmware ● Datapath Logic – Receives 36 bits each TP from two FPGAs on HTR – Bits 0-31 are TP data; bit 35 is BC0; 32-34 are BcN[3:0] – Mapping of TP to RPC outputs stored in BRAM; 256 different mappings selectable by register – RPC Output ● bits 0-23 are TP data ● bits 24-27 BC0, BnC[3:0] ● bits 28-31 are odd parity of groups of 7 bits in 0-27 – All I/Os registered at IOBs to ease timing – Total latency of data path 2.5 clocks

22. Clock domains ● Domain 1: ttc_des_1 – TP data synch'd to this clock ● Domain 2: rx_clk (“low jitter”) – GOLs use this clock ● No FIFO to reduce latency; phase measurement performed at start-up; GOL clock polarity set ● Introduces ½ clock uncertainty in latency (RPC group say not a problem)

23. Local Bus Interface ● Control/status registers of O/SLB ● Interface logic shared between CPLD and FPGA ● Provides access to I2C bus on GOL

24. Firmware Status ● CPLD design complete ● Datapath and basic local bus interface complete ● Occupancy histogram not yet implemented (needs detailed specification) ● Only ~33% logic used in XC3S400 (and a large chip can be fitted if needed)

25. Price / Quantity ● 48 triple-output O/SLBs will be installed ● We plan to start about 75 boards