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1 Models for Hand Analysis NMOS Transistor PMOS Transistor V DSN  V GSN -V TN V DSN  V GSN -V TN V DSP  V GSP -V TP V DSP  V GSP -V TP K N =(W/L)K’

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Presentation on theme: "1 Models for Hand Analysis NMOS Transistor PMOS Transistor V DSN  V GSN -V TN V DSN  V GSN -V TN V DSP  V GSP -V TP V DSP  V GSP -V TP K N =(W/L)K’"— Presentation transcript:

1 1 Models for Hand Analysis NMOS Transistor PMOS Transistor V DSN  V GSN -V TN V DSN  V GSN -V TN V DSP  V GSP -V TP V DSP  V GSP -V TP K N =(W/L)K’ N K P =(W/L)K’ P

2 2 pMOS Current model VDSP>VGSP -VTP VDSP <VGSP-VTP

3 3 Channel Resistance R=

4 4 Variation of resistance with Vgs

5 5 LENGTHL SL/S WIDTHW SW/S THIN OXIDEt ox St ox /S DIFFUSION DOPINGNDND 1/SN D. S SUBSTRATE DOPINGNA 1/SN A. S SUPPLY VOLTAGEV DD 1/S V DD /S Linear Scaling

6 Scalling Effects 6

7 7 Velocity Saturation and mobility Degradation

8 8 TOH’s Model for Short Channel for

9 9 Secondary Effects n Subthreshold current: is the small current that flows from drain at Vgs < Vt n Punch through: If a large voltage is applied to Vds, then the depletion region of the drain can extend to the source, a punch through occurs and under these condition a large current can flow from the drain to source. n Hot carrier: As a results of scaling, device dimensions are reduced while, doping concentrations are increased, while voltages are not reduced to the same proportion, as a consequence there is an increase in electric field in the channel region while, the thickness of the gate insulating layer is thinner. Due to the acceleration of electrons by the Vds, electrons and holes gaining high speed can penetrate the gate insulator and change its characteristics. n Channel hot electrons: If the Vds is increased, then the lateral electric field is increased and the electric field accelerates the electrons near the drain with high kinetic energy they are injected into the oxide near the drain.

10 10 Semiconductor Resistors Resistance R=  ( l /A) = (  /t). ( l /w ) = Rsh. ( l /w ) Rsh = sheet resistance Ω /  For 0.5u process: N+ diffusion : 70 Ω/  M1: 0.06 Ω/  P+ diffusion : 140 Ω/  M2: 0.06 Ω/  Polysilicon : 12 Ω/  M3: 0.03 Ω/  Polycide:2-3 Ω/  P-well: 2.5K Ω/  N-well: 1K Ω/  w current l t (A)

11 11 Semiconductor Resistors Al n+ Diffusion n+ Field oxide polysilicon Polysilicon Resistor Diffusion Resistor SiO2

12 12 Variations in Width and Length W eff W drawn WDWD W D 1. Width Oxide encroachment W eff = W drawn - 2W D 2. Length Lateral diffusion L D = 0.7Xj L eff = L drawn - 2L D L drawn L D L eff L D polysilicon

13 13 Semiconductor Capacitors 1. Poly Capacitor: a. Poly to substrate b. Poly1 to Poly2 2. Diffusion Capacitor n+ (N D ) depletion region substrate (N A ) bottomwall capacitance sidewall capacitances

14 14 Transistor Resistance : Two Components: Drain/ Sources Resistance: R D(S) = Rsh x no. of squares+ contact resistance. Channel Resistance : Depends on the region of operation: L W (D) (S) n+ (G) R S Rch R D Linear Saturation

15 15 Dynamic Behavior of MOS Transistor Prentice Hall/Rabaey

16 16 The Gate Capacitance Prentice Hall/Rabaey

17 17 Average Gate Capacitance Most important regions in digital design: saturation and cut-off Different distributions of gate capacitance for varying operating conditions Prentice Hall/Rabaey

18 18 Diffusion Capacitance Prentice Hall/Rabaey

19 19 Diffusion Capacitance

20 20 SPICE TRANSISTOR MODEL

21 21 SPICE MODELS

22 22 MAIN MOS SPICE PARAMETERS Prentice Hall/Rabaey

23 23 SPICE Parameters for Parasitics Prentice Hall/Rabaey

24 24 SPICE Transistors Parameters Prentice Hall/Rabaey

25 25 Example

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