1. Time-to-Fa ilure Tree KEIHANEH KIA – 94/1/24 1 Alireza Ejlali  Sharif University of Technology  Tehran. Seyyed Ghasem Miremadi  Sharif University of Technology  Tehran.

2. Table of content: What is fault tree? 3 Time to failure tree 4 The building units of time-to-failure trees 6 2-of-3 gate 7 TMR system with a cold spare 8 an FT with cold spare gates 9 Random-selector unit10 tausworthe method12 hardware implementation14 summary & conclusions16 KEIHANEH KIA – 94/1/24 2

3. What is fault tree? Definition: FT is an analytical model of a system. Analyzing method: 1- analytic approaches:  limited in few models and certain kinds of parameter distributions.  fast and computationally cheap. 2- MCS(Monte Carlo simulation):  it can be broadly used.  It is limited by the intensive computation time-consuming. KEIHANEH KIA – 94/1/24 3

4. Time to failure tree  TTF can be used for accelerating MCS using field programmable gate arrays (FPGAs).  By receiving the TTFs of the Components, computes the TTF of the whole system.  Both dynamic and static FTs can be converted into time-to-failure trees. KEIHANEH KIA – 94/1/24 4

5. time-to-failure tree  if the corresponding event (component failure) occursa Boolean variable takes 1. - FT gates process binary values.  parallel system : AND gate MAX.  series system :OR MIN.  SEQ gate : -dynamic gate. - modeling cold spares. - ADD. KEIHANEH KIA – 94/1/24 5

6. Figure 1: The building units of time-to-failure trees, a) Series system, b) Parallel system, c) Cold spare KEIHANEH KIA – 94/1/24 6

7. Figure 2: A 2-of-3 gate is converted to its corresponding time-to-failure unit. KEIHANEH KIA – 94/1/24 7

8. Figure 3: TMR system with a cold spare (a) its FT (b) its time-to-failure tree. KEIHANEH KIA – 94/1/24 8

9. Figure 4 - an FT with cold spare gates can be transformed to FT with a SEQ gate. KEIHANEH KIA – 94/1/24 9

10. Figure 6 : Random-selector unit and the hardware implementation. - This unit is used for modeling the coverage factor KEIHANEH KIA – 94/1/24 10

11. Figure 7: The time-to-failure tree which models a cold spare system with coverage factor = 0.7. KEIHANEH KIA – 94/1/24 11

12. -the Tausworthe method for generating pseudo random numbers that is implemented using an FSR (feedback shift-register). - An FSR generates uniformly distributed random numbers. tausworthe method: KEIHANEH KIA – 94/1/24 12

13. Other distributions: If R has a uniform distribution over [0,1), the random variable X has an exponential distribution: if U has a uniform distribution over [0,1), the random variable X has a Weibull distribution : These functions are implemented as look-up tables using ROM(Read Only Memory) chips KEIHANEH KIA – 94/1/24 13

14. hardware implementation of time-tofailure trees Improvement: - MAX, MIN, ADD, random selector, pseudo random number generators can be easily implemented using digital circuits with FPGA. - Since MCS needs to repeat the same task many times with different samples, a pipeline implementation of time-to-failure trees has been used.  Altera FPGA (EPF10K50RC240) for HW. PC(Pentium III, 933 MHz, RAM=256 MB, OS=Win2000) for executing MCS software. KEIHANEH KIA – 94/1/24 14

15. Figure 13: Pipeline implementation of the time-to-failure tree KEIHANEH KIA – 94/1/24 15

16. SUMMARY & CONCLUSIONS: Fault trees are analyzed using analytic approaches or Monte Carlo simulation. - analytic approaches is limited in few models and certain kinds of parameter distributions. - Monte Carlo simulation can be broadly used. But is time-consuming because of the intensive computation. new model : time-to-failure tree: fault trees time-to-failure trees digital circuit FPGA monte carlo simulation can be significantly accelerated using FPGAS. KEIHANEH KIA – 94/1/24 16

17. QUESTION? KEIHANEH KIA – 94/1/24 17

18. END KEIHANEH KIA – 94/1/24 18