1.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-1 Implementing Sums-of-Products Z A B C D E F We find And-Or structures like this all of the time. Although wiring is simpler, part selection is now harder… A B C D Z E F A B C D Z 2 x 2-input And-Or-Invert3 x 2-input And-Or-Invert

2.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-2 Programmed Array Logic (PAL) PALs support multiple functions of the same inputs Fusable links Fusable links – Links may be “blown”. Once blown, they are permanently open. Complex wiring is replaced with programming Current +- 12V

3.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-3 PAL Example C’CB’BA’A C B A F1F1 F2F2 Program F 1 =A’B’+A’C Blow all unused links Program F 2 =A’BC Leave unused product terms alone (AA’BB’CC’) A’B’ A’C A’BC 0

4.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-4 Schematic Representation of PALs F 1 =DC + D’C’ + BA’ + B’A F 2 =DA + CB’ + D’C’BA DCB A DC D’C’ BA’ B’A DA CB’ 0 D’C’BA x’s mark Connections – Fuses are not blown

5.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-5 The Way Things Are: Real PALs 2 3 V cc GND 4 Output Inversion Ctrl Tristate Buffer I/O pin Input pin

6.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-6 A More General Idea A PLA has complete flexibility of its sum-of- products groupings. Programmable Logic Array A PAL has limits on the arrangement of its sum-of- products groupings. Programmed Array Logic

7.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-7 Sharing Product Terms in a PLA F = ABC + AD + AD G =ABC + ABC + AD H =ABC + BD J = B + AD BACD FGHJ ABC AD BD B

8.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-8 Programming Devices PLAs and PALs are programmed using a special programmer Most devices are erasable Don’t use fuses, but instead electrical methods of programming Erased by exposing to UV light

9.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-9 Macrocells Mux Clock Control Mux Output Control Global Clock Altera Macrocell DQ Memory Interconnect To Other Macrocells Invert Control Pad

10.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-10 CPLDs Complex Programmable Logic Devices Contain from 10-1000 macrocells Each macrocell is equivalent to around 20 gates Support up to 200 I/O pins The key resource in a CPLD is interconnect Tradeoff between space for macrocells and space for interconnect Careful design will limit the connections between macrocells

11.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-11 Electrically Erasable PLDs Conventional PLDs are either One-time programmable UV Erasable Must be placed in a programmer to program them EE PLDs can be programmed and erased in place A small (four wire) connection to a computer is needed Once programmed, will retain program indefinitely Never have to take the chip out of its circuit

12.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-12 Field Programmable Gate Arrays FPGAs are based on Look-up Tables (LUTs) A LUT is simply a representation of a truth table 3-input Look-up Table C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1 FPGAs are just a whole lot of LUTs with lots of interconnect a b c f 1010001110100011 LUT Example: Three-input LUT The function is programmable – any LUT can be programmed to be any function

13.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-13 FPGA Organization a b c f xxxxxxxxxxxxxxxx LUT a b c f xxxxxxxxxxxxxxxx a b c f xxxxxxxxxxxxxxxx a b c f xxxxxxxxxxxxxxxx a b c f xxxxxxxxxxxxxxxx a b c f xxxxxxxxxxxxxxxx I/O1I/O2I/O3I/O4 0011011100110111 1101101011011010

14.  Seattle Pacific University EE 1210 - Logic System DesignProgrammable-14 FPGAs FPGAs are based on SRAM Lose programming when power is turned off Can be programmed by a computer or by a special EPROM Capacity May have up to 10,000,000 gate equivalent Up to 1,200 I/O pins