1. University of Connecticut Virtual Lab Carl DiFederico, Shane Tobey, Kasim Ward Graduate Student Advisor: Qihang Shi Senior Faculty Advisor: Mohammed Tehranipoor Electrical & Computer Engineering

2. All Rights Reserved 2 Hardware Design Moving Forward This coming week we wish to begin ordering parts for benchmarking We wish to burn-age an acceptable percentage of chips We must decide on the temperature we wish to run Can we obtain more chips of the same lot #? Moving forward with the relay hub model A quick comparison has been provided

3. All Rights Reserved 3 Scan-Chain Option Problem Leakage and transient current are analog signals, and will damp over long distance, causing DUT farther away to be damped more than DUT closer to probe in a daisy-chain connection One set of instruments for each DUT infeasible

4. All Rights Reserved 4 Tree Signal Path Tree-like connection for analog signal path, and signal amplification on each board for incoming signal Each layer of boards is exposed to more noise

5. All Rights Reserved 5 Analog Signal Path Use an extra board (Hub) as an expandable control interface from FPGA and Oscilloscope to DUT boards This equalizes noise, removes the need for amplification and removes the need to relay the probe Allows for expandibility

6. All Rights Reserved 6 Moving Forward We must research the running speed and noise in relays, however the concept is sound We are finding there are occasionally communication issues with the COM ports and the hardware, these should be handled if not resolved In addition, the programmer board was not functioning properly although this may also be a COM port issue

7. All Rights Reserved 7 Upcoming Deadlines and Goals Oct. 7 th Oral Proposal Presentation Ordering of parts for test this week Finding 8051s of matching lot #