1. 1200V 4H-SiC MOSFETs for High Efficiency Energy Storage System 2016 Kwangwoon IT Exhibition

2. 2 © Semiconductor- and Nano-Devices Lab., KWU Outline 1. Introduction SiC Power Semiconductor The need for high efficiency grid system ESS Advantages of system ESS PCS using SiC 2. Experimental 2D Simulation of 4H-SiC DMOSFET Fabrication of 4H-SiC DMOSFET 3. Results & Discussion JFET- L JFET Optimization JFET- N JFET Optimization Epi layer - T EPI Optimization P-Well optimization : N P-Well, T P-wel Optimized SiC MOSFET on / off characteristics Si IGBT VS SiC MOSFET in Inverter 4. Conclusions

3. 3 © Semiconductor- and Nano-Devices Lab., KWU Outline 1. Introduction SiC Power Semiconductor The need for high efficiency grid system ESS Advantages of system ESS PCS using SiC 2. Experimental 2D Simulation of 4H-SiC DMOSFET Fabrication of 4H-SiC DMOSFET 3. Results & Discussion JFET- L JFET Optimization JFET- N JFET Optimization Epi layer - T EPI Optimization P-Well optimization : N P-Well, T P-wel Optimized SiC MOSFET on / off characteristics Si IGBT VS SiC MOSFET in Inverter 4. Conclusions

4. 4 © Semiconductor- and Nano-Devices Lab., KWU SiC Power Semiconductor  Si vs SiC Wider band gap Higher thermal conductivity Higher breakdown voltage Fast saturation electron velocity than Si physically. High temperature stability, Low power loss High current handling The reliability of SiC devices in electronic system → high power conversion efficiency, → Smaller in the electronic system.

5. 5 © Semiconductor- and Nano-Devices Lab., KWU Energy Storage System(ESS) classificationapplication Grid system ESS  Solar cell  Wind Turbine  Hydroelectric power plants Uninterruptible power supply (UPS)  Telecommunication  Internet Data Center Residence/ industry ESS  House  Plants  PCS structure of Grid system ESS It uses the ESS electric at the peak time, increases energy efficiency using the required time after saving electric power. ESS can improve the electric power quality through the non-uniform power supply stabilization of renewable energy. It can prevent damage by accident power otage. Ref. WPM 스마트강판소재 vol.11

6. 6 © Semiconductor- and Nano-Devices Lab., KWU Switching Characteristics of Devices classificationcapacity Inverter input voltage SiC DMOSFET Development Goals Solar power For Industry 7.5~30 kW (6-pack) 330~450 V (regularity) 30 KW, regularity 400 V standard V B : >800 V, I F : >12.5 A, R on : < 3.2 Ω Wind power For Industry 8~30 kW (6-pack) 330~450 V (regularity) 30 KW, regularity 400 V standard V B : >800 V, I F : >12.5 A, R on : < 3.2 Ω  FET common use device and Device development goals used in PCS inverter  existing inverter based Si IGBT SiC inverter based DMOSFET By reducing Conduction loss and switching loss, Improve the PCS efficiency. Switching loss decrease Conduction loss

7. 7 © Semiconductor- and Nano-Devices Lab., KWU Outline 1. Introduction SiC Power Semiconductor The need for high efficiency grid system ESS Advantages of system ESS PCS using SiC 2. Experimental 2D Simulation of 4H-SiC DMOSFET Fabrication of 4H-SiC DMOSFET 3. Results & Discussion JFET- L JFET Optimization JFET- N JFET Optimization Epi layer - T EPI Optimization P-Well optimization : N P-Well, T P-wel Optimized SiC MOSFET on / off characteristics Si IGBT VS SiC MOSFET in Inverter 4. Conclusions

8. 8 © Semiconductor- and Nano-Devices Lab., KWU Research Target of SiC DMOSFET ESS system inverter (30 KW) used Si IGBT change to 4H-SiC DMOSFET (V B : >1200 V, I F : >12.5 A, R on : <3.2 Ω) To apply PCS inverter ESS Improved efficiency of the system The grid system ESS for high efficiency development of 1200V 4H SIC DMOSFET

9. 9 © Semiconductor- and Nano-Devices Lab., KWU DMOSFET Structure Design ③ ④ ① ②  Structural Design Optimization ① JFET Region length [L JFET ] - L JFET ↑ V B ↓ (oxide breakdown ↑) ② JFET Region doping concentration [N JFET ] - N JFET ↑ R on ↓, V B ↓ ③ thickness of Epi Layer [t Epi ] - t epi ↑ R on ↑, V B ↑ ④ P-well Region doping and thickness [N P-well, t P-well ] - t P-well ↑ V B ↑ - N P-well ↑ R on ↑, V B ↑  DMOSFET includes the high resistance of the JFET region  The minimization of resistance of epilayer ↔ Higher breakdown voltage  Tradeoff in the design is important.

10. 10 © Semiconductor- and Nano-Devices Lab., KWU Fabrication of SiC DMOSFET [1/2] 9/19 Low diffusion coefficients of impurities in SiC → Ion implantation is considered as a suitable solution in SiC

11. 11 © Semiconductor- and Nano-Devices Lab., KWU Fabrication of SiC DMOSFET [2/2] Activation annealing has been demonstrated to be effective to reduce implantation-induced damage and to improve electrical activation of implanted ions in SiC.

12. 12 © Semiconductor- and Nano-Devices Lab., KWU Outline 1. Introduction SiC Power Semiconductor The need for high efficiency grid system ESS Advantages of system ESS PCS using SiC 2. Experimental 2D Simulation of 4H-SiC DMOSFET Fabrication of 4H-SiC DMOSFET 3. Results & Discussion JFET- L JFET Optimization JFET- N JFET Optimization Epi layer - T EPI Optimization P-Well optimization : N P-Well, T P-wel Optimized SiC MOSFET on / off characteristics Si IGBT VS SiC MOSFET in Inverter 4. Conclusions

13. 13 © Semiconductor- and Nano-Devices Lab., KWU JFET optimization: L JFET Semiconductor- & Nano- Device Lab. JFET Region L JFET : 1µm~5µm N JFET : 5X10 15 cm -3 Epi : 5E15cm -3 P-well : 0.5μm, 2E17cm -3 N + source : 0.2μm, 5E19cm -3 N JFET : 5X10 16 cm -3 - 13 -  L JFET Modulation : 1 ~ 5 μm * L JFET = 1 μm in case, because of Depletion region On-current decrease. L JFET (μm)1234 5 V B (V) 440420430440430 R ON,SP (mΩ∙cm 2 ) 11.09.518.968.688.57 V TH (V) 8.528.578.59 FOM (MW/cm 2 ) 11.719.4321.5921.2721.57  JFET region length design is important to reduce on-resistance  Figure of merit : maximum ~21.59MW/cm 2,  Optimizing L JFET is 3μm.

14. 14 © Semiconductor- and Nano-Devices Lab., KWU JFET optimization: N JFET Epi : 5E15cm -3 P-well : 0.5μm, 2E17cm -3 N + source : 0.2μm, 5E19cm -3 JFET Region L JFET : 3µm N JFET : 5X10 15 ~1X10 18 - 14 -  N JFET Modulation : 5X10 16 ~ 1X10 18 cm -3 N JFET (cm -3 )5X10 15 5X10 16 1X10 17 5X10 17 1X10 18 V B (V) 440 430280 R ON,SP (mΩ∙cm 2 ) 10.29.329.199.059.01 V TH (V) 8.62 8.618.16 FOM (MW/cm 2 ) 18.920.7521.0420.4218.7  JFET region design has to be prevented from current saturation in DMOSFET.  Figure of merit : maximum ~21.04MW/cm 2,  Optimizing N JFET is 1x10 17 /cm 3

15. 15 © Semiconductor- and Nano-Devices Lab., KWU Epi layer optimization: T EPI Semiconductor- & Nano- Device Lab. Nepi : 5E15cm -3 P-well : 0.5 μ m, 2E17cm -3 N + source : 0.2 μ m, 5E19cm -3 Channel length : 2 μ m T epi : 6µm ~ 12µm - 15 -  T epi Modulation : 6 ~ 15 μm T EPI (μm)6101215 V B (V) 430500520530 R ON,SP (mΩ∙cm 2 ) 9.8710.610.910.7 V TH (V) 8.508.488.468.70 FOM (MW/cm 2 ) 17.6118.1619.6217.20  To avoid punch-through → High Breakdown voltage  L JFET : 3μm, N JFET : 1x10 17 /cm 3  Figure of merit : maximum ~19.62MW/cm 2,  Optimizing T epi is 12um.

16. 16 © Semiconductor- and Nano-Devices Lab., KWU P-Well optimization : N P-Well, T P-well Semiconductor- & Nano- Device Lab. Epi : 5E15/cm 3 P-well : 2E17/cm 3 N + source : 0.2μm, 5E19/cm 3 Channel length : 2μm t P-Well : 0.4µm ~ 0.7µm Np-Well : 1X10 17 ~7X10 17  V B (V)  FOM (MW/cm 2 ) 0.40.50.60.8 1X10 17 50130185580 2X10 17 57056010001880 3X10 17 570123018802290 5X10 17 14702270 7X10 17 2260 t P-Wel l Np-Well  t P-Well Modulation : 0.4µm ~ 0.7µm, N p-well Modulation : 1X10 17 ~ 7X10 17 /cm 3 0.40.50.60.8 1X10 17 1.44x10 -2 9.38x10 -2 1.83x10 -1 1.69 2X10 17 1.431.574.851.61x10 1 3X10 17 1.436.461.47x10 1 2.07x10 1 5X10 17 1.022.43X10 -3 2.43x10 -3 7X10 17 1.01x10 -9 8.75x10 -10 1.12x10 -9 t P-Wel l Np-Well 1200V 2000V 960.0 0 1920 2400 11.44 18.04 0 2.200 4.400 6.600 8.800 11.00 13.20 15.40 17.60 19.80 22.00

17. 17 © Semiconductor- and Nano-Devices Lab., KWU Optimized SiC MOSFET on / off characteristics Optimized SiC MOSFET on / off characteristics On-resistance R on (mΩ) Breakdown Voltage V B (V) Threshold Voltage V th (V) 32310256 V Voltage step : 5 V Voltage range : 0~1300 V Compliance : 10 mA  Breakdown voltage : > 700 V (@10 mA)  Leakage current : 10 -8 ~ 10 -9 A (@100 V) Voltage step : 0.5 V Voltage range : 0 ~ 15 V Compliance : 15 A  Drain Current : > 10 A  Threshold voltage : ~4.5 V [Area device 16 mm 2 ] Voltage step : 3 V Voltage range : 0~10 V Compliance : 8 A  V B : >800 V, I F : >12.5 A, R on : <3.2 Ω Measurement results

18. 18 © Semiconductor- and Nano-Devices Lab., KWU Inverter circuit: Si IGBT vs. SiC MOSFET  6-pack inverter module (Si IGBT to replace the SiC MOSFET) Inverter Input Voltage Si IGBTSiC MOSFET 450V V B : 1200 V R on 56 Ω A: 5.71 x 4.53 mm 2 V B : 1200 V V th : 2.6V A: 4.83 x5.21 mm 2 Output Current 18A38A Input Voltage 450V Output Power 8.1kW17.1kW Input : DC 450V  Si IGBT Module  SiC MOSFET Module By using SiC MOSFET, compared with Si IGBT, makes 2 times higher output per same device area (25mm 2 )

19. 19 © Semiconductor- and Nano-Devices Lab., KWU Outline 1. Introduction SiC Power Semiconductor The need for high efficiency grid system ESS Advantages of system ESS PCS using SiC 2. Experimental 2D Simulation of 4H-SiC DMOSFET Fabrication of 4H-SiC DMOSFET 3. Results & Discussion JFET- L JFET Optimization JFET- N JFET Optimization Epi layer - T EPI Optimization P-Well optimization : N P-Well, T P-wel Optimized SiC MOSFET on / off characteristics Si IGBT VS SiC MOSFET in Inverter 4. Conclusions

20. 20 © Semiconductor- and Nano-Devices Lab., KWU Conclusions SiC FETs were designed and fabricated for high efficiency grid Energy Storage System. We optimezed SiC DMOSFET structures by using 2D-physics based simulator by modulating dimensions and doping concentrations in JFET region, epilayer and p-well region. The performance of experimentally fabricated SiC DMOSFETs exhibit excellent performances. R on : ~323 mΩ, V B : ~1250V, V th : ~6V. SiC MOSFETs are shown to be superior to Si devices with higher efficiency in power control unit: output power of SiC MOSFET was ~2 times higher than that of Si IGBT at the same device area (25mm 2 ), even without considering high- speed switching Moreover, the abillity of SiC DMOSFETs to operate at higher temperatures and lower switching loss, will enable further improved performances.