1. Design a MIPS Processor (II)
Instruction set overview of MIPS processors
Single cycle MIPS processor
Datapath design
Controller design
Multiple cycle MIPS Processor
finite state machine; sequencer; microcode.
Design a Multiple cycle MIPS Processor with Verilog at Behavioral/Structural Level (Project 5)

2. The Multicycle Datapath with Control Signals
PCWriteCond
PCWrite
PCSource
IorD
ALUOp
MemRead
Control
ALUSrcB
MemWrite
ALUSrcA
MemtoReg
RegWrite
IRWrite
RegDst
PC[31-28]
Instr[31-26]
Shift
left 2 28
Instr[25-0] 2 1
Address
Memory PC
Read Addr 1
Read
Data 1 A IR
Register
File 1 1
zero
Read Addr 2
Read Data
(Instr. or Data)
ALUout
ALU
Write Addr
Write Data 1
Read
Data 2 B
MDR 1
Write Data 4 1 2
Instr[15-0]
Sign
Extend
Shift
left 2 3 32
ALU
control
Instr[5-0]

3. Five Execution Steps Instruction Fetch
Instruction Decode and Register Fetch
Execution, Memory Address Computation, or Branch Completion
Memory Access or R-type Instruction Completion
Memory Read Completion (Write-back) INSTRUCTIONS TAKE FROM CYCLES!

4. Operations in Each Step

6. ALU Controller Main Control Op code 6 ALU (Local) func 2 ALUop ALUctr3
ALUop is 2-bit wide to represent:
“I-type” requiring the ALU to perform:
(00) add for load/store and (01) sub for beq
“R-type” (10), need to reference func field
to ALU op rs rt rd
shamt
funct 6 11 16 21 26 31
R-type
R-type lw sw
beq
jump
ALUop (Symbolic)
“R-type”
Add
Subtract
xxx
ALUop<1:0> 10 00 01

7. ALUctr
ALU Operation
funct<5:0>
Instruction Operation
add
subtract
and or
set-on-less-than
0000
AND
0001 OR
0010
add
0110
sub
0111
set-on-less-than
ALUop
func
ALU
Operation
ALUctr
bit<1>
bit<0>
bit<5>
bit<4>
bit<3>
bit<2>
bit<1>
bit<0>
bit<3>
bit<2>
bit<1>
bit<0> lw sw
beq R x x x x 1 x 1 x
Add 1 1 x x x
Add 1 1 x x x
Subtract 1 1
Add 1 1
Subtract 1 1
And 1 1 1 Or 1 1 1 1 1
Set on < 1 1 1

8. Logic Equation for ALUctr
ALUop
func
ALUctr
bit<1>
bit<0>
bit<5>
bit<4>
bit<3>
bit<2>
bit<1>
bit<0>
bit<3>
bit<2>
bit<1>
bit<0> x x x x x x 1 x 1 x x x x x x 1 1 1 x x x 1 1 x x x 1 1 1 1 x x x 1 1 x x x 1 1 1 1 x x x 1 1 1 1 1

9. Logic Equation for ALUctr2
ALUop
func
bit<1>
bit<0>
bit<5> x
bit<4> x
bit<3>
bit<2> x
bit<1> x 1
bit<0> x
ALUctr<2> x 1 x 1 1 x 1 1 x 1 1
This makes a case for don’t care
ALUctr2 = ALUop0 + ALUop1‧func2’‧func1‧func0’

10. Logic Equation for ALUctr1
ALUop
func
bit<1>
bit<0>
bit<5> x
bit<4>
bit<3> x 1
bit<2> x
bit<1> x 1
bit<0> x
ALUctr<1> x 1 x 1 x 1 x x 1 x x 1 x x
ALUctr1 = ALUop1’ + ALUop1‧func2’‧func0’

11. Logic Equation for ALUctr0
ALUop
func
bit<1>
bit<0>
bit<5> x
bit<4> x
bit<3> 1
bit<2> 1
bit<1> 1
bit<0> 1
ALUctr<0> 1 x 1 1 x 1
ALUctr0 = ALUop1‧func3’‧func2‧func1’‧func0
+ ALUop1’‧func3‧func2’‧func1‧func0’

13. Control Signals from the Main Control Unit
Signal name Effect when deasserted Effect when asserted ALUSrcA 1st ALU operand = PC 1st ALU operand = Reg[rs] RegWrite None Reg file is written MemtoReg Reg. data input = ALU Reg. write data input = MDR RegDst Reg. write dest. no. = rt Reg. write dest. no. = rd MemRead None Memory at address is read MemWrite None Memory at address is written IorD Memory address = PC Memory address = ALUout IRWrite None IR = Memory PCWrite None PC = PCSource PCWriteCond None If zero then PC = PCSource
Signal name Value Effect ALUOp 00 ALU adds ALU subtracts ALU operates according to func code ALUSrcB 00 2nd ALU input = B nd ALU input = nd ALU input = sign extended IR[15-0] nd ALU input = sign ext., shift left 2 IR[15-0] PCSource 00 PC = ALU (PC + 4) PC = ALUout (branch target address) PC = PC+4[31-28] || IR[25-0] << 2
Single Bit Control
Multiple Bit Control

14. The Multicycle Datapath with Control Signals
PCWriteCond
PCWrite
PCSource
IorD
ALUOp
MemRead
Control
ALUSrcB
MemWrite
ALUSrcA
MemtoReg
RegWrite
IRWrite
RegDst
PC[31-28]
Instr[31-26]
Shift
left 2 28
Instr[25-0] 2 1
Address
Memory PC
Read Addr 1
Read
Data 1 A IR
Register
File 1 1
zero
Read Addr 2
Read Data
(Instr. or Data)
ALUout
ALU
Write Addr
Write Data 1
Read
Data 2 B
MDR 1
Write Data 4 1 2
Instr[15-0]
Sign
Extend
Shift
left 2 3 32
ALU
control
Instr[5-0]

16. Truth Table input output op S Datapath control NS
xxxx
xxxx

17. From FSM to Truth Table Output Equation PCWrite state0 + state9
PCWriteCond state8
IorD state3 + state5
… …
NextState0 state4 + state5 + state7 + state8
+state9
NextState1 state0
NextState2 state1  ((op = ‘lw’) + (op = ‘sw’))
NextState3 state2  (op = ‘lw’)
… ...
Output Current states
PCWrite
PCWriteCond
IorD
… …

20. 4-bit Next State: {NS3, NS2, NS1, NS0}
NS0 is 1 for the following next state 0001, 0011, 0101, 0111, 1001

23. PLA Implementation

24. ROM Implementation
Need a ROM of 10-bit address, 20-bit word (16-bit datapath control, 4-bit next state)
Address ROM content
op S Datapath control NS

25. ROM Implementation(Truth Table)
Address ROM content
op S Datapath control NS
xxxx
xxxx
Could break up into
two smaller ROMs

27. ROM vs PLA ROM: use two smaller ROMs (Fig. C.3.7, C.3.8)
4 state bits give the 16 outputs, 24x16 bits of ROM
10 bits (op + state) give 4 next state bits, 210x 4 bits of ROM
Total = 4.3K bits of ROM (compared to 210x 20 bits of single ROM implementation)
PLA is much smaller
can share product terms
only need entries that produce an active output
can take into account don't-cares
Size is (#inputs  #product-terms) + (#outputs  #product-terms) For this example = (10x17)+(20x17) = 460 PLA cells
PLA cells usually about the size of a ROM cell (slightly bigger)

28. Use Counter for Sequence Control

29. Address Select Unit AddrCtl Value: 0 Set state to 0 1 Dispatch ROM 1
3 Use incremented state

33. “microprogrammed control”
Controller Design Review
Several possible initial representations, sequence control and logic representation, and control implementation => all may be determined indep. Initial Rep. Finite State Diagram Microprogram
Sequencing Explicit Next State Microprogram
Control Function Counter +
Dispatch ROMs Logic Rep. Logic Equations Truth Tables
Implementation PLA ROM
“hardwired control”
“microprogrammed control”

34. Microprogram Control is the hard part of processor design
Datapath is fairly regular and well-organized
Memory is highly regular
Control is irregular and global
But, the state diagrams that define the controller for an instruction set processor are highly structured
Use this structure to construct a simple “microsequencer”
Control reduces to programming this simple device
=> microprogramming
sequencer
control
datapath control
microinstruction
…..
control
signals
micro-PC
sequencer

35. Microinstruction Control signals :
Think of the set of control signals that must be asserted in a state as an instruction
Executing a microinstruction has the effect of asserting the control signal specified by the microinstruction
Sequencing
What microinstruction should be executed next ?
Execute sequentially (next state unconditionally)
Branch (next state also depends on inputs)
A microprogram is a sequence of microinstructions executing a program flow chart (finite state machine)

36. Designing a Microinstruction Set
1) Start with a list of control signals
2) Group signals together that make sense (vs. random): called fields
3) Places fields in some logical order (e.g., ALU operation & ALU operands first and microinstruction sequencing last)
4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set control signals
Use computers to design computers
5) To minimize the width, encode operations that will never be used at the same time

37. Control Signals

38. The Microprogram

39. The Controller

40. The Dispatch ROMs
Rformat1
JUMP1
BEQ1
Mem1
Mem1
LW2
SW2