1. Ketil Røed University of Bergen - Department of Physics Ketil Røed MSc student, microelectronics University of Bergen Norway Irradiation tests of Altera SRAM-based FPGA -and fault tolerant design concepts

2. Introduction and motivation Test facility and setup Upset detection Results Fault-tolerant design efforts Conclusion OUTLINE

3. drift gas 90% Ne – 10%CO 2 Largest ever: 88 m 3 570.000 channels 18 regions on each side 6 readout sections in each region 216 RCU cards ALICE – Time Projection Chamber TPC

4. Ketil Røed University of Bergen - Department of Physics Electronics -Located in experiment environment -Exposed to radiation generated by the particle collisions Single Event Upsets -Due to the energy deposited by an ionizing particle Q: Are the electronic components radiation tolerant ? Need for Radiation test Motivation Front end electronics, RCU

5. Test Facilities and setup Ongoing activity at the Oslo Cyclotron, Department of Physics, University of Oslo (Jon Wikne and Evind A. Olsen) Scanditronix MC-35 Ketil Røed University of Bergen - Department of Physics

6. Ketil Røed University of Bergen - Department of Physics Test Facilities and setup

7. RCU – Readout Control Unit ( Prototype II) Irradiation tests of different electronic components My focus is on the FPGA Ketil Røed University of Bergen - Department of Physics CONTROL LOGIC (FPGA: APEX 20K400) SRAM Test Facilities and setup

8. Ketil Røed University of Bergen - Department of Physics Test Facilities and setup Cables

9. Upset detection Ketil RøedUniversity of Bergen - Department of Physics Typical 6 transistor SRAM cell Single Event Upset ● High-energetic particles induces nuclear reactions in the silicon (E > 20 MeV - protons, neutrons, pions) ● Not enough charge deposited through direct ionization to cause a SEU ● Heavy recoil ions from reactions ionizes the material (electron-hole pairs) ● Leads to a change in state of a transistor (SEU) -Soft error – can be corrected (rewriting or reprogramming) Two types of concern ● Upsets in configuration SRAM cells ● Single bitflips The APEX20K400E offers no direct readout of configuration SRAM -Indirectly detection of configuration upset through a VHDL design Error observed reflects a change in logic due to a configuration upset, and not the configuration upset itself

10. Upset detection Possibility of undetectable configuration upsets!! -Not 100% usage of SRAM bits --> some upset may not influence logic -Test results gives and estimate of configuration upsets. First glance – configuration upsets and single bitflips induced in logic look the same -Distinguishable by looking at them over time -Configuration upset: Permanent until reprogramming of device -Single upsets: Limited in time, present until next clock cycle Task: design hardware that detects SEU's in both logic and internal RAM blocks of the device VHDL design -32 bit wide and 400 bit long shiftregister implemented in logic elements (approx. 90% of the LEs) -32 bit wide and 4096 bit deep FIFO implemented in internal RAM blocks (approx 60% of the internal RAM bits)

11. Upset detection Serial Slow Control Network SCSN FPGA A fixed pattern is shifted through and compared for setups when read out. Communication through SCSN (Slow Control Serial Network) - Introduces problem of SEUs in the SCSN Software on Linux PC to read out and analyse data (C, Matlab) Data in Data out Serial Slow Control Network SCSN Ketil Røed University of Bergen - Department of Physics 0000000 1000000 0100000 0010000 0001000 0000100 0000010 0000001 0000000. 0000000 1000000 0100000 0010000 0001000 0000100 0000010 0010001 0000000. 0000000

12. FIFO in internal RAM Shiftregister in logic elements Example of analyzing data Single upset Configuration upset

13. Test procedure Oslo Cyclotron ● 29 MeV external proton beam ● Beam intensities > 10pA (flux : 0.6x10^8 protons/s cm²) ● Beamsport 1 x 1cm ● Beam distribution made uniform by defocusing and using a gold foil placed upstream in beampath. Ketil Røed University of Bergen - Department of Physics Device under test ALTERA APEX EP20K400E (FPGA) ● 1.8V ● 0.18um ● 8-Layer aluminium process ● Typical number of gates is 400000 ● 16640 LE's ● 212992 RAM bits

14. Preliminary results Observations Configuration upsets in logic and internal RAM Single upsets in internal RAM only ● Many interconnection in logic elements ● Low density of SRAM cells compared to internal RAM blocks - SEU - uncorrelated - Expecting linear dependency

15. Cross-Section Cross-section: 1.9x10^10 +- 0.8x10^10 cm^2 - Expecting constant value - Should be independent of flux

16. Fault-tolerant design efforts Ketil Røed University of Bergen - Department of Physics FPGA’s has become more complex over the last few years -Whole system on one device -Different fault-tolerant design techniques has to be considered for control functions and the data storage circuits -FIFO,RAM etc – For instance Hamming coding for detection and correction of data points (Can live with a few lost data points) -Registers, state machines, control logic – Coding techniques for detection and correction and redundancy if a part of the circuit fails. -For redundancy – need to think of space requirements!

17. Conclusion More experienced leading to better understanding and more certain results in the near future Ketil Røed University of Bergen - Department of Physics Configuration upsets Logic 1.9x10^-10 +- 0.8x10^-10 cm^2 Internal RAM 1.5x10^-10 +- 0.8x10^-10 cm^2 Single upsets Logic < 5.3x10^-12 cm^2 Internal RAM 4.1x10^-10 +- 2.2x10^-10 cm^2 Latest estimated maximum radiation flux of: 250 particles/cm^2 s  0.3-1.2 upsets per 8 ALICE hour per 216 device (8 hours – one ALICE run) More and better calculations will be done More irradiation tests to support results and collect better statistics

18. VHDL-design Standard test procedure – better correlation between different tests Continue developing the shiftregister based design Interfacing the FPGA Route the shiftregister directly to the pins of the FPGA without any internal communicatin control like the SCSN network Fault tolerant design concepts Continue work on different types of coding techniques which will satisfy the systems demand for detecting and correcting SEUs. Outlook University of Bergen - Department of Physics Ketil Røed

19. University of Bergen - Department of Physics THE END! K. Ullaland, D.Röhrich, K.Røed University of Bergen, Norway B.Skaali, J.Wikne, E.Olsen University of Oslo, Norway V.Lindenstruth,H.Tilsner S.Martens KIP, University of Heidelberg, Germany Marc Stockmaier Physikalisches Institut, University of Heidelberg Luciano Musa Cern

20. Field Programmable Gate Array FPGA vs ASIC ? -FPGAs are fully programmable alternative to customized chips (ASIC) -Shortens the development time Programmed using high level languages such as VHDL and Verilog Architecture 2 dimensional array of reconfigurable logic blocks Logic block – can be a combination of simple logic gates, multiplexers, look up tables and flip-flops. The configuration of the logic blocks are controlled by Static RAM cells SRAM cells are distributed throughout the FPGA (Can not be read out and verified for the ALTERA APEX20K400) FPGA Ketil Røed University of Bergen - Department of Physics

21. Typical 6 transistor SRAM cell FPGA – Radiation effects Electronics -Located in experiment environment -Exposed to radiation generated by the particle collisions Single Event Upsets Due to the energy deposited by a single particle Soft error – can be corrected To types -Bitflip in configuration SRAM – cause functional failure -Bitflip in a register – restored after one clock cycle Need for Irradiation tests Ketil Røed University of Bergen - Department of Physics 216 FPGAs ???

22. Front end electronics, RCU Time projection Chamber

24. FPGA Data in Data out SCSN 0000000 1000000 0100000 0010000 0001000 0000100 0000010 0000001 0000000. 0000000 1000000 0100000 0010000 0001000 0000100 0000010 0010001 0000000. 0000000