1. 1 HOLA status – February 2011 ● What's been done: ● Firmware for Cyclone IV FPGA for Tang's board – Emulation of TLK2501 transmission protocol – Flow control from either DAQ or FTK ● Timing closure (per static TimeQuest analysis) ● Got familiar with SOLAR/FILAR device drivers & user libraries that we can use to set up a test stand ● What needs to be done: ● Finish up a full FEMB/LSC/LDC/ROMB testbench in Modelsim ● Test on practice synchronization with TLK2501 ● Build a test stand and run stress tests

2. 2 FIFO D[32] @ 40 MHz D[32] @ 50 MHz Big picture: old LSC core Interface to TLK TLK2501 chip (LSC side) FPGA TLK2501 chip (DAQ LDC) Serial connection (via optical transceiver) FPGA provides a parallel interface to an outside SERDES device (TLK-2501), which feeds serial signal to an optical transmitter. Note that TLK-2501 alone costs more than the entire FPGA that we are planning to use. (only forward channel shown) D[16] + 2 control lines @ 100 MHz

3. 3 FIFO D[32] @ 40 MHz D[32] @ 50 MHz Big picture: new LSC core Interface to TLK ALTGX wrapper FPGA D[16] + 2 control lines @ 100 MHz Serial connections (via optical transceiver) (only forward channel shown) TLK2501 chip (FTK LDC) TLK2501 chip (DAQ LDC) OLD LSC CORE (altera SERDES megafunction) TX_CL K The original LSC core is slightly modified: ● ALTGX fetches data into the phase comp FIFO using a special clock (TX_CLK), propagated back to the LSC core ● For better metastability protection, 50 MHz clock made related to TX_CLK ● Flow control from FTK (see a later slide)

4. 4 Old LSC core ALTGX wrapper Differential transmitter pins (DAQ & FTK) Differential receiver pins TLK interface What the top-level entity looks like

5. 5 What the ALTGX wrapper looks like ALTG X tx wrapper Emulation of TLK2501 transmission rx wrapper Interpreting data from TLK2501 (one per channel – DAQ and FTK)

6. 6 Checking functionality of tx wrapper: Checking functionality of rx wrapper:

7. 7 FIFO D[32] @ 40 MHz D[32] @ 50 MHz Big picture: XOFF and return channel XOFF basically acts as a READ-ENABLE for the main data FIFO. It blocks further data transmission until the receiver of the data (LDC & ROMB) informs us that the data can be sent again. While XOFF is asserted, the link will be sending IDLE's downstream. For the new LSC core, we have two return channels (from trigger and FTK). Either one will be able to set XOFF (in other words, it's a logical-OR). Note that the new LSC core will only look for XOFF/XON on the FTK return channel, and will ignore all other return channel codes from FTK. READ-ENABLE / XOFF

8. 8 Resource Utilization ● All available transmitters and receivers ● 2/3 PLLs ● One for the transceiver block ● Another for internal frequency halving ● Around 10% of logic elements ● 0.5% of internal RAM ● Can use the rest for test patterns FPGA floor plan

9. 9 Supplemental slides (some details about transceivers)

10. 10 Transceiver datapath Lock byte boundary by detecting a 10-bit comma character from TLK2501 Since comma always appears in LSB byte, we can also use it to establish byte order Circled in RED: 8b/10b encoder/decoder and CDR unit. 8b/10b is required to maintain high transition density in the received data stream. It also provides a basic error detection mechanism – see next page.

11. 11 8b/10b ● 256 8-bit characters => 1024 10-bit characters ● Larger 10-bit phase space => ● Select mappings with {5/5,6/4,4/6} bit parity ● E.g, 0011001111 – 6/4, sent if “RD-” ● Every 6/4 or 4/6 has a complement: ● E.g, 1100110000 – 4/6, sent if “RD+” ● To maintain overall DC balance and uniform transition density, RD+ and RD- alternate ● Error detection: unused 10-bit code OR disparity violation.

12. 12

13. 13 TLK2501 synchronization TLK2501 only synchronizes on this comma In order to guarantee that K28.5 commas with correct disparity are received by TLK synchronization circuit, the first IDLE must be selected judiciously depending on running disparity. If a wrong IDLE is sent (e.g., /I2/ after RD+ or /I1/ after RD-), TLK receiver will assert error on received data.

14. 14 ALTGX 8b/10b limitation ● 8b/10b encoder does not provide running disparity, so we can't send the correct IDLE Altera has an 8b/10b megafunction that support 16b/20b cascading, but it is not free (from one of Altera implementation guides)

15. 15 Alternative lookup-based solution ALTGX provides optional interface to force running disparity to an arbitrary value Flip LUT data[8 ] clk disparity_flippe d Tells whether the encoded version of this 8bit word would flip running disparity Given 16-bit data from LSC core, the upper and lower 8 bits are simultaneously sent to two flip LUTs. One clock later, we receive corresponding disparity_flipped bits. Together with running disparity in the end of last 16-bit data block, they tell us: ● Disparity encoding for upper and lower 8 bits of current word ● Running disparity in the end of transmission of current 16-bit word

16. 16 Supplemental slides (other)

17. 17 Timing closure No red here = good

18. 18 Transceiver reset sequence Transmission is easy: just need PLL to lock Reception is more complicated. In the end, we wait for CDR's to lock Wrote an FSM for the reset sequence, but discovered that “reset on power-on” coupled with altgx_reconfig is sufficient to synchronize transceivers on the Altera test board. Therefore, this reset sequence is not included in the current version of the firmware.

19. 19 8b/10b logic implementation 8b/10b map is usually implemented as a complex network of gates. This was the subject of a 1984 patent from IBM. 16b/20b implementation is the subject of more recent patents (2007) A simpler option is a MRAM-based lookup table for the entire mapping. But this would take up ~10% of Cyclone IV resources. For this reason, we chose to utilize an existing 8b/10b module from Altera, but provide our own disparity calculation