1. EMT 351/4 DIGITAL IC DESIGN Verilog Behavioral Modeling  Constructs for Activity Flow Control  Task & Function  System Tasks for Timing Checks

2. CONSTRUCTS FOR ACTIVITY FLOW CONTROL Procedural control statements modify the activity flow within a behavior by determining whether: Procedural control statements modify the activity flow within a behavior by determining whether: 1. To select or branch among alternative statements – (? … :, case, if) 2. Execute certain computations repeatedly – (repeat, for, while, forever) 3. Suspend activity flow for a specified time or until a condition has been met – (wait) 4. Branch into parallel activity flow – (fork … join) 5. Terminate execution of a task – (disable)

3. ACTVITY FLOW CONTROL 1. To select or branch among alternative statements – using conditional operator (? … :) module mux_behavior (y_out, clock, reset, sel, a, b); input clock, reset, sel; input [15:0] a, b; output [15:0] y_out; reg [15:0] y_out; always @ (posedge clock or negedge reset) if (reset == 0) y_out = 0; else y_out = (sel) ? a+b : a-b; endmodule

4. ACTVITY FLOW CONTROL 1. To select or branch among alternative statements – using case statement (case) module mux4_case (a,b,c,d,select,y_out); input a,b,c,d; input [1:0] select; output y_out; reg y_out; always @ (a or b or c or d or select) begin case (select) 0 : y_out = a; 1 : y_out = b; 2 : y_out = c; 3 : y_out = d; default y_out = 1’bx; endcase end endmodule

5. ACTVITY FLOW CONTROL 1. To select or branch among alternative statements – using conditional statement (if … else) module mux4_if (a,b,c,d,select,y_out); input a,b,c,d; input [1:0] select; output y_out; reg y_out; always @ (a or b or c or d or select) begin if (select == 00) y_out = a; else if (select == 01) y_out = b; else if (select == 10) y_out = c; else y_out = d; end endmodule

6. ACTVITY FLOW CONTROL 2. Execute certain computations repeatedly – using repeat loop module repeater (clk,outA); input clk; output outA; reg inA; reg outA; initial begin inA = 1; #100 inA = 0; #50 inA = 1; #50 inA = 0; #200; end initial begin outA = repeat (3) @ (posedge clk) inA; end endmodule

7. ACTVITY FLOW CONTROL 2. Execute certain computations repeatedly – using for loop module ANDgate_tb (); reg inputA, inputB; wire outputA; integer i; initial begin for (i=0; i<4; i=i+1) begin {inputA, inputB} = i; #10; end ANDgate ANDgate_inst (inputA, inputB, outputA); endmodule

8. ACTVITY FLOW CONTROL 2. Execute certain computations repeatedly – using forever loop ……. parameter half_cycle = 100; initial begin: clock_loop forever begin #half_cycle_clock = 0; #half_cycle_clock = 1; end; end endmodule

9. ACTVITY FLOW CONTROL 3. Suspend activity flow for a specified time or until a condition has been met – using wait statement module wait_sample (a,b,en,y1,y2); input a,b,en; output y1,y2; reg y1,y2; always begin wait (en) y1 = a; #100 y2 = b; #100; end endmodule

10. ACTVITY FLOW CONTROL 4. Branch into parallel activity flow – using fork … join statement Fork... Join syntax does not supported by synthesis tools Fork... Join syntax does not supported by synthesis tools Conveniently supports waveform generation for tb Conveniently supports waveform generation for tb Once the fork…join statement execute, all of the following activity cannot be executed until fork…join statement is complete Once the fork…join statement execute, all of the following activity cannot be executed until fork…join statement is complete … fork #50 sig_wave = ‘b1; #100 sig_wave = ‘b0; #150 sig_wave = ‘b1; #300 sig_wave = ‘b0; join ……

11. ACTVITY FLOW CONTROL 5. Terminate execution of a task – using disable statement module find_first_one (A_word,trigger,index_value); input [15:0] A_word; input trigger; output [3:0] index_value; reg [3:0] index_value; always @ (trigger) begin index_value = 0; for (index_value=0; index_value<=15; index_value=index_value+1); if (A_word[index_value]==1) disable; end endmodule

12. TASKS AND FUNCTIONS Verilog has two types of sub-programs: Verilog has two types of sub-programs: Tasks Tasks - Create hierarchical organization of the procedural statements within a Verilog behavior Functions Functions - Only can be implemented using combinational behavior Tasks and functions let designers manage a smaller segment of code Tasks and functions let designers manage a smaller segment of code Able to improve the readability, portability and maintainability of code Able to improve the readability, portability and maintainability of code

13. TASKS Need to declared within a module and referenced only from within a behavior Need to declared within a module and referenced only from within a behavior Can have parameters passed to it, and the results can be passed back to the environment Can have parameters passed to it, and the results can be passed back to the environment All the inputs and outputs declared in a task will be associated with the inputs and outputs declared in a module according to the order All the inputs and outputs declared in a task will be associated with the inputs and outputs declared in a module according to the order A task must be named, and may include declarations of any number or combination of the following: A task must be named, and may include declarations of any number or combination of the following: - parameter, input, output, inout, reg, integer, real, time, realtime and event

14. Example 1 Multiple 4-bit bitwise operation module bitwise.. …. reg [3:0] AB_and, AB_or, AB_xor; reg [3:0] A, B; always @ (A or B) begin bitwise_optn (AB_and, AB_or, AB_xor, A, B); end task bitwise_optn output [3:0] AB_and, AB_or, AB_xor; input A, B; begin # 5AB_and = A & B; AB_or = A |B; AB_xor = A ^ B; endendtask….endmodule

15. module bit_counter (dataword, bit_count); input [7:0] dataword; output [3:0] bit_count; reg [3:0] bit_count; always @ (dataword) count_ones_in_word (dataword, bit_count); task count_ones_in_word; input [7:0] reg_a; output [3:0] count; reg [3:0] count; reg [7:0] temp_reg; begin count = 0; count = 0; temp_reg = reg_a; temp_reg = reg_a; while (temp_reg) while (temp_reg)begin count = count + temp_reg[0]; count = count + temp_reg[0]; temp_reg = temp_reg >> 1; temp_reg = temp_reg >> 1;endendendtaskendmodule Example 2 Number of 1’s counter

16. Simulation result for no. of 1’s counter Cont..

17. FUNCTIONS Compute only value on the basis of the present value of the parameters passed into the function Compute only value on the basis of the present value of the parameters passed into the function May not contain timing controls such as: May not contain timing controls such as: - delay control, event control, wait statement Also may not invoke a task within a function Also may not invoke a task within a function Must be declared within a module, and may contain declaration of inputs and local variables Must be declared within a module, and may contain declaration of inputs and local variables Implemented by expression and returns a value to the original location Implemented by expression and returns a value to the original location May not have any declaration of output or inout May not have any declaration of output or inout Must have at least one input argument Must have at least one input argument

18. Example 3 Left & Right bit shifter module shifter… … reg [7:0] addr, left_addr, right_addr; reg control; always @ (addr) begin left_addr = shift (addr, 0); right_addr = shift (addr, 1); end function [7:0] shift; input [7:0] address; input control; begin shift = (control == 0) ? (address > 1); endendfunctionendmodule

19. module word_aligner (word_in,word_out); input [7:0] word_in; output [7:0] word_out; assign word_out = aligned_word (word_in); function [7:0] aligned_word; input [7:0] aligned_word; begin aligned_word = word_in; aligned_word = word_in; if (aligned_word != 0) if (aligned_word != 0) while (aligned_word[7] == 0) aligned_word = aligned_word << 1; while (aligned_word[7] == 0) aligned_word = aligned_word << 1;endendfunctionendmodule Example 4 Word Aligner

20. Cont.. Simulation result of word aligner

21. Task vs. Function Task Task A task can enable other task & function A task can enable other task & function Tasks may execute in non- zero simulation time Tasks may execute in non- zero simulation time Tasks may contain delay, event, or timing control statements Tasks may contain delay, event, or timing control statements Task may have zero or more arguments of type input, output or inout Task may have zero or more arguments of type input, output or inout Tasks do not return with a value, but can pass multiple values thru output & inout arguments Tasks do not return with a value, but can pass multiple values thru output & inout arguments Function Function A function can enable another function, but not task Function always execute at 0 simulation time Functions may not contain any delay, event, or timing control statements Functions must have at least 1 input argument – can have more than 1 input Functions always return a single value – cannot have output / inout arguments

22. SYSTEM TASKS FOR TIMING CHECKS There are 2 basic forms of timing analysis: There are 2 basic forms of timing analysis: Static analysis – considers the structural topology of a circuit, enumerates the paths along which signals can propagate, and determines whether certain timing constraints are met Static analysis – considers the structural topology of a circuit, enumerates the paths along which signals can propagate, and determines whether certain timing constraints are met Dynamic analysis – verifies the timing of a circuit through simulation Dynamic analysis – verifies the timing of a circuit through simulation

23. SYSTEM TASKS FOR TIMING CHECKS Static analysis Static analysis Advantages Advantages 1. Considers all possible paths thru the circuit 2. Does not miss reporting a timing violation Disadvantage Disadvantage 1. May generate timing reports on “false paths” in the circuit Dynamic analysis Dynamic analysis Advantage Advantage 1. Only good as the stimulus set used to simulate the circuit Disadvantages Disadvantages 1. Timing violation can be missed if the stimulus set fails to exercise all functional paths 2. Does not report false alarms 3. Become less practical and reliable for global verification when apply for huge circuits

24. SYSTEM TASKS FOR TIMING CHECKS Setup and hold conditions Setup and hold conditions $setup (data, posedge clk, 5)

25. SYSTEM TASKS FOR TIMING CHECKS Setup and hold conditions Setup and hold conditions $hold (data, posedge clk, 2)

26. SYSTEM TASKS FOR TIMING CHECKS Setup and hold conditions Setup and hold conditions $setuphold (data, posedge clk, 5, 2)

27. SYSTEM TASKS FOR TIMING CHECKS Signal period Signal period Used to check whether the period of a signal is sufficiently long Used to check whether the period of a signal is sufficiently long $period (posedge clock_a, t_limit)

28. SYSTEM TASKS FOR TIMING CHECKS Minimum pulse width Minimum pulse width To check the width of the active edge pulse of the clock signal must not be too small To check the width of the active edge pulse of the clock signal must not be too small $width (posedge clock_a, t_mpw)

29. SYSTEM TASKS FOR TIMING CHECKS Signal skew Signal skew Used to denote the time interval between reference features of two waveforms Used to denote the time interval between reference features of two waveforms $skew (negedge clk1, negedge clk2, t_skew)