1. CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-4 Verification 1Created by: Ms.Amany AlSaleh

2. 2  Verification - shows that the final circuit designed implements the original specification: Manual logic analysis. Computer simulation program.  Prevents incorrect circuit designs from being manufactured and used.  Simple specifications are: truth tables Boolean equations HDL code  If the above result from formulation and are not the original specification, it is critical that the formulation process be flawless for the verification to be valid! Verification Given Logic Circuit Diagram Boolean Function Truth Table Find Created by: Ms.Amany AlSaleh

3. 3 Basic Verification Methods  Manual Logic Analysis Find the truth table or Boolean equations for the final circuit Compare the final circuit truth table with the specified truth table, or Show that the Boolean equations for the final circuit are equal to the specified Boolean equations  Simulation Simulate the final circuit (or its netlist, possibly written as an HDL) and the specified truth table, equations, or HDL description using test input values that fully validate correctness. The obvious test for a combinational circuit is application of all possible “care” input combinations from the specification Created by: Ms.Amany AlSaleh

4. 4 1) Derivation of Boolean Functions: 1.Label all gate outputs in level 1 + determine their Boolean functions. 2.Label all gate outputs in the following level + determine their Boolean functions. 3.Repeat step 2 until you reach circuit output. Manual Logic Analysis Created by: Ms.Amany AlSaleh

5. 5 T1=BC T2=AB F2=T5=AB+D F1=T3+T4 = A+BC+ABD+AD+BD T1 T2 T3 T4 T5 4 Input Variables Derivation of Boolean Functions T3=A+T1 = A+BC T5=T2+D = AB + D T4=T2  D = (AB)  D = ABD+AD+BD Created by: Ms.Amany AlSaleh

6. 6 1) Derivation of the Truth Table  Determine the number of input variables in the circuit. For n inputs, list the binary numbers from 0 to 2n –1 in the table.  Break the circuit into small single-output blocks by labeling each block output with an arbitrary symbol.  Obtain the truth table for the blocks with functions that depend on input variables only.  Proceed to obtain truth table for blocks with functions that depend on previously defined inputs and block outputs, until the columns for all circuit outputs are determined. Manual Logic Analysis (Cont.) Created by: Ms.Amany AlSaleh

7. 7 T2 T1 T3 XY XZ YZ Derivation of the Truth Table Problem: Verify that the circuit below forms the arithmetic sum of the three bits at inputs X, Y, and Z. Created by: Ms.Amany AlSaleh

8. 8 Derivation of the Truth Table Created by: Ms.Amany AlSaleh

9. 9 Manual Logic Analysis (Cont.) 2) Compare the final circuit truth table with the specified truth table  Example: Binary Adder X Y ZCS 00000 00101 01001 10001 01110 11010 10110 11111 Number of Ones = 0 Number of Ones = 1 Number of Ones = 2 Number of Ones = 3 Created by: Ms.Amany AlSaleh

10. 10 Verification Example: Manual Analysis  BCD-to-Excess 3 Code Converter 1.Find the SOP Boolean equations from the final circuit. 2.Find the truth table from these equations 3.Compare to the formulation truth table Created by: Ms.Amany AlSaleh

11. 11 Verification Example: Manual Analysis  Finding the Boolean Equations: T = C D = C + D W = A (T B) = A + B T = A + B (C + D) = A + BC + BD X = (B T) (B C D) = B T + B T = B (C + D) + B (C + D) = BC + BD + BCD Y = CD + T = CD + (C + D) = CD + CD Z = D Created by: Ms.Amany AlSaleh

12. 12 BCD-to-Excess 3 Code Converter 2. Find the circuit truth table from the equations and compare it to specification truth table: The tables match! Created by: Ms.Amany AlSaleh

13. 13 Verification Example: Simulation  Simulation procedure: Using a computer permits truth-table verification to be done for a significantly larger number of variables and greatly reduces the tedious analysis effort required. Steps are: 1.Use a schematic editor or text editor to enter a gate level representation of the final circuit. 2.Use a waveform editor or text editor to enter a test consisting of a sequence of input combinations to be applied to the circuit. This test should guarantee the correctness of the circuit if the simulated responses to it are correct. Short of applying all possible “care” input combinations, generation of such a test can be difficult. Created by: Ms.Amany AlSaleh

14. 14 Verification Example: Simulation (Cont.)  Enter BCD-to-Excess-3 Code Converter Circuit Schematic Created by: Ms.Amany AlSaleh

15. 15 Verification Example: Simulation (Cont.) 2. Enter waveform that applies all possible input combinations:  Are all BCD input combinations present? (Low is a 0 and high is a one)  Yes, 0000 through 1001 are present. Created by: Ms.Amany AlSaleh

16. 16 Verification Example: Simulation (Cont.) 3. Run the simulation of the circuit for 120 ns  Do the simulation output combinations match the original truth table?  Yes, the output combinations 0011 through 1100 occur in response to 0000 through 1001, respectively. Created by: Ms.Amany AlSaleh