CSE 331 Computer Organization and Design Fall 2007 Week 10 & 11

CSE 331 Computer Organization and Design Fall 2007 Week 10 & 11
Section 1: Mary Jane Irwin ( Section 2: Krishna Narayanan Course material on ANGEL: cms.psu.edu [adapted from D. Patterson slides]

Head’s Up Last week’s material This week’s material and next week’s
Designing a MIPS single cycle datapath This week’s material and next week’s More on single cycle datapath design and exam review Reading assignment – PH: 5.4, B.8, C.1-C.2 Multicycle MIPS datapath implementation Reading assignment – PH: 5.5, B.10 The week after Exam #2 material Finish multicycle MIPS datapath and control path implementation Reading assignment – PH: 5.7, B.10, C.3-C.5 Reminders Exam #1 take home solution due Thursday, Nov 1st (by 11:55pm) HW 7 is due Tuesday, Nov 27th (by 11:55pm) Quiz 6 closes Tuesday, Nov 5th (by 11:55pm) Exam #2 is Thursday, Nov 8th, 6:30 to 7:45pm People with conflicts should have sent by now Friday, Nov 16th is the late-drop deadline Final Exam is Tuesday, Dec 18th, 10:10 to noon, 112 Walker

Each MAS (microarchitectural specifications) included
Pipeline and block diagrams Textual description of the theory of operation Unit inputs and outputs and protocols governing data transfers Corner cases of the design that were especially tricky New circuits required for implementation Notes on testing and validation The Pentium Chronicles, Colwell, pg. 82

Review: Creating a Datapath from the Parts
Assemble the datapath elements, add control lines as needed, and design the control path Fetch, decode and execute each instructions in one clock cycle – single cycle design no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., one reason why we have a separate Instruction Memory and Data Memory) to share datapath elements between two different instruction classes need multiplexors at the input of the shared elements with control lines to do the selection Cycle time is determined by length of the longest (slowest) path

Review: A Simple MIPS Datapath Design
Read Address Instruction Memory Add PC 4 Shift left 2 Add PCSrc RegWrite ALUSrc ALU control MemWrite MemtoReg ovf zero Read Addr 1 Read Data 1 Address Register File Read Addr 2 Data Memory Read Data ALU Write Addr Read Data 2 Write Data Write Data MemRead Sign Extend 16 32

Adding the Control Selecting the operations to perform (ALU, Register File and Memory read/write) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction R-type: 31 25 20 15 5 op rs rt rd funct shamt 10 Observations op field always in bits 31-26 addr of two registers to be read are always specified by the rs and rt fields (bits and 20-16) base register for lw and sw always in rs (bits 25-21) addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions offset for beq, lw, and sw always in bits 15-0 I-Type: op rs rt address offset 31 25 20 15

(Almost) Complete Single Cycle Datapath
Add Add 1 4 Shift left 2 PCSrc RegDst 1 Register File Read Data 1 Data 2 RegWrite Sign Extend 16 32 ALUSrc MemWrite MemtoReg ovf zero Instr[25-21] Read Addr 1 Instruction Memory Address Instr[20-16] Read Addr 2 Data Memory Read Address PC Instr[31-0] Read Data 1 ALU Write Addr Instr[ ] Write Data Write Data 1 ALU control ALUOp Instr[5-0] Instr[15-0] MemRead

ALU Control ALU's operation based on instruction type and function code ALU control input Function 0000 and 0001 or 0010 xor 0011 nor 0110 add 1110 subtract 1111 set on less than Notice that we are using different encodings than in the book

ALU Control, Con’t Controlling the ALU uses of multiple decoding levels main control unit generates the ALUOp bits ALU control unit generates ALUcontrol bits Instr op funct ALUOp action ALUcontrol lw xxxxxx 00 sw beq 01 add 100000 10 0110 subt 100010 subtract 1110 and 100100 0000 or 100101 0001 xor 100110 0010 nor 100111 0011 slt 101010 1111 For class handout

ALU Control, Con’t Controlling the ALU uses of multiple decoding levels main control unit generates the ALUOp bits ALU control unit generates ALUcontrol bits Instr op funct ALUOp action ALUcontrol lw xxxxxx 00 sw beq 01 add 100000 10 0110 subt 100010 subtract 1110 and 100100 0000 or 100101 0001 xor 100110 0010 nor 100111 0011 slt 101010 1111 add 0110 subtract 1110 For lecture Note that unsigned operations are not included. So there is no way to disable the overflow flag within the ALU. But you have have the centralized control do that, based on mo of the function field.

ALU Control Truth Table
F5 F4 F3 F2 F1 F0 ALU Op1 ALU Op0 ALU control3 ALU control2 ALU control1 ALU control0 X 1 For class handout Four, 6-input truth tables

ALU Control Truth Table
Our ALU m control input F5 F4 F3 F2 F1 F0 ALU Op1 ALU Op0 ALU control3 ALU control2 ALU control1 ALU control0 X 1 For lecture Add/subt Mux control Four, 6-input truth tables

ALU Control Logic From the truth table can design the ALU Control logic Instr[3] Instr[2] Instr[1] Instr[0] ALUOp1 ALUOp0 ALUcontrol3 ALUcontrol2 ALUcontrol3 = ALUOp0 or !F2 F1 ALUOp1 ALUcontrol2 = !F2 ALUOp1 or !ALUOp1 ALUcontrol1 = !F2 ALUOp1 or !ALUOp1 or F1 ALUOp1 ALUcontrol0 = F0 ALUOp1 or F3 ALUOp1 ALUcontrol1 ALUcontrol0

(Almost) Complete Datapath with Control Unit
Add Add 1 4 Shift left 2 PCSrc ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] Read Data 1 ALU Write Addr Read Data 2 1 Note mux control inputs have been swapped (for three of the muxes) from the last picture to be consistent with the book. Write Data Instr[ ] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

Main Control Unit Instr RegDst ALUSrc MemReg RegWr MemRd MemWr Branch ALUOp R-type 000000 lw 100011 sw 101011 beq 000100 For class handout Completely determined by the instruction opcode field Note that a multiplexor whose control input is 0 has a definite action, even if it is not used in performing the operation

R-type Instruction Data/Control Flow
Add Add 1 4 Shift left 2 PCSrc ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] Read Data 1 ALU Write Addr Read Data 2 1 For class handout – have a student come forward and mark the connections in the datapath that are active. And show the state of the control lines. Write Data Instr[ ] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

R-type Instruction Data/Control Flow
Add Add 1 4 Shift left 2 PCSrc ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] Read Data 1 ALU Write Addr Read Data 2 1 For lecture Write Data Instr[ ] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

Store Word Instruction Data/Control Flow

Load Word Instruction Data/Control Flow

Branch Instruction Data/Control Flow

Main Control Unit Instr RegDst ALUSrc MemReg RegWr MemRd MemWr Branch ALUOp R-type 000000 1 10 lw 100011 00 sw 101011 X beq 000100 01 For class handout Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design (could have to be 0 or could be a X (don’t care))

Control Unit Logic From the truth table can design the Main Control logic Instr[31] Instr[30] Instr[29] Instr[28] Instr[27] Instr[26] R-type lw sw beq RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0

Review: Handling Jump Operations
Jump operation have to replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits 31 J-Type: op jump target address Add 4 4 Jump address Instruction Memory Shift left 2 28 Read Address PC Instruction 26

Adding the Jump Operation
Instr[25-0] 1 Shift left 2 28 32 26 PC+4[31-28] Add Add 1 4 Shift left 2 PCSrc Jump ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] Read Data 1 ALU Write Addr For class handout Read Data 2 1 Write Data Instr[ ] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

Adding the Jump Operation
Instr[25-0] 1 Shift left 2 28 32 26 PC+4[31-28] Add Add 1 4 Shift left 2 PCSrc Jump ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegWrite RegDst ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] Read Data 1 ALU Write Addr For lecture Good exam questions Add jalr rs,rd 0 rs 0 rd 0 9 jump to instr whose addr is in rs and save addr of next inst (PC+4) in rd Add the PowerPC addressing modes of update addressing and indexed addressing (will have to expand the RegFile to be three read port and two write port) Add andi, ori, addi - have to have both a signextend and a zeroextend and choose between the two, will have to augment the ALUop encoding (since can’t get the op information out of the funct bits as with R-type) Add mult rs, rt with the result being left in hi|lo - so also include the mfhi and mflo instructions (will have to add a multiplier, the hi and lo registers and then a couple of muxes and their control). Add barrel shifter Read Data 2 1 Write Data Instr[ ] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

Main Control Unit Instr RegDst ALUSrc MemReg RegWr MemRd MemWr Branch ALUOp Jump R-type 000000 lw 100011 sw 101011 beq 000100 j 000010 For class handout Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

Main Control Unit Instr RegDst ALUSrc MemReg RegWr MemRd MemWr Branch ALUOp Jump R-type 000000 1 10 lw 100011 00 sw 101011 X beq 000100 01 j 000010 XX For class handout Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

End of First Lecture of the Week

Need another Colwell quote or Dilbert here

Single Cycle Implementation Cycle Time
Unfortunately, though simple, the single cycle approach is not used because it is very slow Clock cycle must have the same length for every instruction What is the longest (slowest) path (slowest instruction)?

Instruction Critical Paths
Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except: Instruction and Data Memory (4 ns) ALU and adders (2 ns) Register File access (reads or writes) (1 ns) Instr. I Mem Reg Rd ALU Op D Mem Reg Wr Total R-type load store beq jump For class handout

Instruction Critical Paths
Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires, setup and hold times) except: Instruction and Data Memory (4 ns) ALU and adders (2 ns) Register File access (reads or writes) (1 ns) Instr. I Mem Reg Rd ALU Op D Mem Reg Wr Total R-type load store beq jump 4 1 2 8 For lecture Note that PC is updated during I Mem read 4 1 2 12 4 1 2 11 4 1 2 7 4

Single Cycle Disadvantages & Advantages
Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instr especially problematic for more complex instructions like floating point multiply May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but It is simple and easy to understand Clk lw sw Waste Cycle 1 Cycle 2 In the Single Cycle implementation, the cycle time is set to accommodate the longest instruction, the Load instruction. Since the cycle time has to be long enough for the load instruction, it is too long for the store instruction so the last part of the cycle here is wasted.

Multicycle Implementation Overview
Each instruction step takes 1 clock cycle Therefore, an instruction takes more than 1 clock cycle to complete Not every instruction takes the same number of clock cycles to complete Multicycle implementations allow faster clock rates different instructions to take a different number of clock cycles functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result only need one memory only need one ALU/adder

The Multicycle Datapath – A High Level View
Registers have to be added after every major functional unit to hold the output value until it is used in a subsequent clock cycle IR MDR A B Address Memory Read Addr 1 PC Read Data 1 Register File Read Addr 2 ALUout Read Data (Instr. or Data) ALU Write Addr Write Data Read Data 2 Note extra registers added – IR, MDR, A, B, and ALUout Write Data

Clocking the Multicycle Datapath
System Clock MemWrite RegWrite clock cycle Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Data 2 ALU IR MDR A B ALUout Note extra registers added – IR, MDR, A, B, and ALUout

Our Multicycle Approach
Break up the instructions into steps where each step takes a clock cycle while trying to balance the amount of work to be done in each step use only one major functional unit per clock cycle At the end of a clock cycle Store values needed in a later clock cycle by the current instruction in a state element (internal register not visible to the programmer) IR – Instruction Register MDR – Memory Data Register A and B – Register File read data registers ALUout – ALU output register All (except IR) hold data only between a pair of adjacent clock cycles (so they don’t need a write control signal) Data used by subsequent instructions are stored in programmer visible state elements (i.e., Register File, PC, or Memory)

The Complete Multicycle Data with Control
PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 1 Address Memory PC Read Addr 1 A IR Read Data 1 Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) ALUout ALU Write Addr For class handout Write Data 1 Read Data 2 B MDR 1 Write Data 4 1 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

Review: Our ALU Control
Controlling the ALU uses of multiple decoding levels main control unit generates the ALUOp bits ALU control unit generates ALUcontrol bits Instr op funct ALUOp action ALUcontrol lw xxxxxx 00 add 0110 sw beq 01 subtract 1110 100000 10 subt 100010 and 100100 0000 or 100101 0001 xor 100110 0010 nor 100111 0011 slt 101010 1111 For lecture Note that unsigned operations are not included. So there is no way to disable the overflow flag within the ALU. But you have have the centralized control do that, based on mo of the function field.

Our Multicycle Approach, con’t
Reading from or writing to any of the internal registers, Register File, or the PC occurs (quickly) at the beginning (for read) or the end of a clock cycle (for write) Reading from the Register File takes ~50% of a clock cycle since it has additional control and access overhead (but reading can be done in parallel with decode) Had to add multiplexors in front of several of the functional unit input ports (e.g., Memory, ALU) because they are now shared by different clock cycles and/or do multiple jobs All operations occurring in one clock cycle occur in parallel This limits us to one ALU operation, one Memory access, and one Register File access per clock cycle

Five Instruction Steps
Instruction Fetch Instruction Decode and Register Fetch R-type Instruction Execution, Memory Read/Write Address Computation, Branch Completion, or Jump Completion Memory Read Access, Memory Write Completion or R-type Instruction Completion Memory Read Completion (Write Back) INSTRUCTIONS TAKE FROM CYCLES!

Step 1: Instruction Fetch
Use PC to get instruction from the memory and put it in the Instruction Register Increment the PC by 4 and put the result back in the PC Can be described succinctly using the RTL "Register-Transfer Language“ IR = Memory[PC]; PC = PC + 4; Note that the incremented PC is also stored in the ALUout register, but this action is benign Can we figure out the values of the control signals? What is the advantage of updating the PC now?

Datapath Activity During Instruction Fetch

Datapath Activity During Instruction Fetch
PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 1 Address Memory PC Read Addr 1 A IR Read Data 1 Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) ALUout ALU Write Addr For lecture Write Data 1 Read Data 2 B MDR 1 Write Data 4 1 2 00 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

Fetch Control Signals Settings
Instr Fetch Start For class handout

Fetch Control Signals Settings
IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X Start For lecture

Step 2: Instruction Decode and Register Fetch
Don’t know what the instruction is yet, so can only Read registers rs and rt in case we need them Compute the branch address in case the instruction is a branch The RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC (sign-extend(IR[15-0])<< 2); Note we aren't setting any control lines based on the instruction (since we don’t know what it is (the control logic is busy "decoding" the op code bits))

Datapath Activity During Instruction Decode

Decode Control Signals Settings
IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X Start For class handout

Decode Control Signals Settings
IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 Start For lecture

Step 3 (instruction dependent)
ALU is performing one of four functions, based on instruction type Memory reference (lw and sw): ALUOut = A + sign-extend(IR[15-0]); R-type: ALUOut = A op B; Branch: if (A==B) PC = ALUOut; Jump: PC = PC[31-28] || (IR[25-0] << 2);

Datapath Activity During lw & sw Execute

Datapath Activity During R-type Execute

Datapath Activity During beq Execute

Datapath Activity During j Execute

Datapath Activity During j Execute
PCWriteCond PCWrite PCSource IorD ALUOp MemRead Control ALUSrcB MemWrite ALUSrcA MemtoReg RegWrite IRWrite RegDst PC[31-28] Instr[31-26] Shift left 2 28 Instr[25-0] 2 1 Address Memory PC Read Addr 1 A IR Read Data 1 Register File 1 1 zero Read Addr 2 Read Data (Instr. or Data) ALUout ALU Write Addr For lecture Write Data 1 Read Data 2 B MDR 1 Write Data 4 1 2 Instr[15-0] Sign Extend Shift left 2 3 32 ALU control Instr[5-0]

Execute Control Signals Settings
Decode IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 Start (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) Execute For class handout

Execute Control Signals Settings
Decode IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Instr Fetch Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 Start (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 PCSource=10 PCWrite Execute For lecture

Where We are Headed After Exam #2
Finish the design of the multi-cycle machine Step 4 and step 5 data path design control path design for the multi-cycle machine a microprogramming approach for control path design Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Data 2 ALU IR MDR A B ALUout

CSE 331 Computer Organization and Design Fall 2007 Week 10 & 11

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