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Access the Instruction from Memory
PC Address Next PC Logic Instruction Memory Simplified Overview Instruction Access the Instruction from Memory
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Access the Data from Registers
PC Address Next PC Logic Instruction Memory Simplified Overview Instruction Register File Access the Data from Registers
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Perform the Instruction
PC Address Next PC Logic Instruction Memory Simplified Overview Instruction Register File ALU Perform the Instruction
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Write the Result PC Next PC Logic Address Instruction Memory
Simplified Overview Instruction Addr Register File Data Memory ALU Data Out Data In Write the Result
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PC Next PC Logic Address Instruction Memory Simplified Overview
Register File Data Memory ALU Data Out Data In Timing Assumption
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MIPS - Lite Consider the following instructions for implementation INSTRUCTION OP FUNCT R type op rs, rt, rd add subtract AND OR set on less than 0 42 load word na lw rt, imm(rs) store word na sw rt, imm(rs) branch equal 4 na beq rs, rt,imm
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Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT R1 R2 Rw Registers R1 R2 Rw Dw Dr1 Dr2
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Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs R1 rt R2 rd Rw Registers R1 R2 Rw Dw Dr1 Dr2
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Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs R1 rt x R2 rd rt Rw Registers R1 R2 Rw Dw Dr1 Dr2
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Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs R1 rt x rt R2 rd rt x Rw Registers R1 R2 Rw Dw Dr1 Dr2
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Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw Registers R1 R2 Rw Dw Dr1 Dr2
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RegDst = Register Destination for the Write Register
Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw Registers rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register
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RegDst = Register Destination for the Write Register
Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw x x RegDst rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register
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RegWrite = Write the selected register with Write Data Input
Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw x x RegDst RegWrite = Write the selected register with Write Data Input rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register
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1 1 0 0 RegWrite = Write the selected register with Write Data Input
Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw x x RegDst RegWrite = Write the selected register with Write Data Input rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register
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PC Next PC Logic Address Instruction Memory Simplified Overview
Register File Data Memory ALU Data Out Data In
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ALU Operation Control Lines
ALU Control Code Function Bnegate Operation and or add subtract set on less than
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ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add 0 32
subtract AND OR set on less than load word na store word na branch equal na
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ALUOp = 10 if the operation depends on the funct field 00 if add
ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add subtract AND OR set on less than load word na store word na branch equal na ALUOp = 10 if the operation depends on the funct field 00 if add 01 if subtract
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ALUOp = 10 if the operation depends on the funct field 00 if add
ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control add add subtract subtract AND and OR or set on less than slt load word na add store word na add branch equal na subtract ALUOp = 10 if the operation depends on the funct field 00 if add 01 if subtract
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ALU Control INSTRUCTION OP FUNCT ALUOp ALU Action ALU control
add add subtract subtract AND and OR or set on less than slt load word na add store word na add branch equal na subtract
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ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm add lw sw beq Input a b Zero a b ALU Result ALU control funct ALUOp
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ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm add lw sw beq Input Dr1 Dr2 a b Zero a b ALU Result ALU control funct ALUOp
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Load Word & Store Word ( I – type )
lw rt, imm16 (rs) or sw rt, imm16 ( rs) op rs rt imm16 lw # load word M[ R[rs] + sign_ext(imm16) ] R[rt] sw # store word R[rt] M[ R[rs] + sign_ext(imm16) ]
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ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) a b Zero a b ALU Result ALU control funct ALUOp
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ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) Dr1 Dr2 a b Zero a b ALU Result ALU control funct ALUOp
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ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) Dr1 Dr2 a b Zero Dr1 a b ALU Result Dr2 1 sign ext imm 6 ALU control ALUSrc funct ALUOp
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ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) Dr1 Dr2 a b ALUSrc = ALU second reg control Dr1 a b Zero ALU Result Dr2 1 sign ext imm 6 ALU control ALUSrc funct ALUOp
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ALU Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm add lw sw beq Input Dr1 Dr2 Dr1 ext(imm) Dr1 Dr2 a b ALUSrc = ALU second reg control Dr1 a b Zero ALU Result Dr2 1 sign ext imm 6 ALU control ALUSrc funct ALUOp
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PC Next PC Logic Address Instruction Memory Simplified Overview
Register File Data Memory ALU Data Out Data In
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Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm MemWrite Result Addr Dr Dr2 Dw MemRead Data Memory
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1 1 0 0 RegWrite = Write the selected register with Write Data Input
Register File Control add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq INPUT rs rs rs rs R1 rt x rt rt R2 rd rt x x Rw x x RegDst RegWrite = Write the selected register with Write Data Input rs rt rd R1 R2 Rw Dw Dr1 Dr2 1 mux RegDst = Register Destination for the Write Register
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Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control MemWrite MemRead MemWrite Result Addr Dr Dw Dr2 Data Memory MemRead
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Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control MemWrite MemRead MemWrite Result Addr Dr Dw Dr2 Data Memory MemRead
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Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs) beq rs, rt, imm add lw sw beq Control MemWrite MemRead MemWrite Result Addr Dr Dw Dr2 Data Memory MemRead
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Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm add lw sw beq Control MemWrite MemRead MemtoReg mux MemWrite 1 to Register File Dw Result Addr Dr Dw Dr2 MemtoReg Selects data memory or ALU output to Register Write Data Data Memory MemRead
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Data Memory add rd, rs, rt lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm add lw sw beq Control MemWrite MemRead MemtoReg x x mux MemWrite 1 to Register File Dw Result Addr Dr Dw Dr2 MemtoReg Selects data memory or ALU output to Register Write Data Data Memory MemRead
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PC Next PC Logic Address Instruction Memory Simplified Overview
Register File Data Memory ALU Data Out Data In
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add rd, rs, rt PC Arithmetic lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm PC Arithmetic 4 ALU 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 ? imm16 sign ext 16 32
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add rd, rs, rt PC Arithmetic lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm PC Arithmetic 4 ALU 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 imm16 sign ext Zero 16 32 Branch
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add rd, rs, rt PC Arithmetic lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm PC Arithmetic add lw sw beq Control Branch 4 ALU 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 imm16 sign ext Zero 16 32 Branch
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add rd, rs, rt PC Arithmetic lw rt, imm(rs) sw rt, imm(rs)
beq rs, rt, imm PC Arithmetic add lw sw beq Control Branch 4 ALU 1 Instr Mem Addr PC+4 PC ALU Shift Left 2 imm16 sign ext Zero 16 32 Branch
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Control Summary Inputs R type lw sw beq Op Outputs RegDst x x ALUSrc MemtoReg x x RegWrite MemRead MemWrite Branch ALUOp ALUOp
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Review Fig 4.15 page 320 / Fig. 4.17 page 322
Review Timing
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Add Jump Instruction j Label go to Label op address 2 address
6 bits bits The complete 32 bit address is : address 00 4 bits bits bits Upper 4 bits of the Program Counter, PC jump uses word addresses address * 4 = address:00 This is Pseudodirect Addressing. Note: 256 MB word boundaries
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Jump Instruction Data Path
28 32 shift left 2 address Instruction[25-0] : 1 PC+4 (31-28) 4 4 “Other” Next Instr Logic Add PC
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Jump Instruction Data Path
Jump = Opcode(2) Jump 28 32 shift left 2 address Instruction[25-0] : 1 PC+4 (31-28) 4 4 “Other” Next Instr Logic Add PC
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