2. Test 2 Fall 2007 Post Mortem Topics Sequential Circuits November 20, 2007 CSCE 211 Digital Design

3. – 2 – CSCE 211H Fall 2007 1. Draw State Diagram Draw the state diagram for a coke machine that takes quarters and dimes (no nickels) and has two buttons C and D to select either cokes or diet dr. peppers. Assume to encourage loss of weight the management has decided cokes are $.50 and diet dr. peppers are $.35. Assuming no change is given.

4. – 3 – CSCE 211H Fall 2007

5. – 4 – CSCE 211H Fall 2007 1b. How many inputs are there? $.10, $.25, C (coke), D (dr. pepper) 1c. How many rows in the transition table would there be? 8 or 9 states  log 2 #states = #bits to encode state = 3 or 4 #rows = 2 #Inputs + #BitsForState = 2 7 or 2 8 = 128 or 256 1d. How many inputs bits are necessary if you use an encoder? two

6. – 5 – CSCE 211H Fall 2007 2. State diagram  Transition Table x s0s1 s2 s3 d=1 d=0 d=1 d=0 d=1 Current State Input d Next State S00S2 S01S1 S10S1 S11S0 S20S3 S21S2 S30S0 S31S3 State table

7. – 6 – CSCE 211H Fall 2007 2b. 2 flip-flops ABdAB 00010 00101 01001 01100 10011 10110 11000 11111 Current state Next state Input s0s1 s2 s3 d=1 d=0 d=1 d=0 d=1 s0 s1 s2 s3

8. – 7 – CSCE 211H Fall 2007 3. Excitation Tables Given the transition Table XYNext State Q(t+1) 000 01Q(t) 10Q’(t) 111

9. – 8 – CSCE 211H Fall 2007 3. Excitation Tables  Excitation of X-Y flip-flop Q(t)Q(t+1)XYComment 000X No change 01 or reset 00 011X Set 11 or complement 10 10X0 Reset 00 or complement 10 11X1 No change 01 or set 11

10. – 9 – CSCE 211H Fall 2007 3c. Excitation for JK and D Q(t)Q(t+1)JKComment 000X No change 00 or reset 01 011X Set 10 or complement 11 10X1 Reset 01 or complement 11 11X0 No change 00 or set 10 Q(t)Q(t+1)D000 011 100 111 A race condition is when the outputs of a circuit feedback to the inputs and change the output which again feedback and change the output …

11. – 10 – CSCE 211H Fall 2007 4. Transition  excitation table using JK ABCXABC JAKA 00000010X 00010100X 00100100X 00110110X 01000110X 01011001X 01101001X 01111011X 1000101X0 1001110X0 1010110X0 1011111X0 1100111X0 1101000X1 1110000X1 1111001X1 Current state Next state Input Flip-flop inputs

12. – 11 – CSCE 211H Fall 2007 4. Transition  excitation table using D ABCXABCDA 00000010 00010100 00100100 00110110 01000110 01011001 01101001 01111011 10001011 10011101 10101101 10111111 11001111 11010000 11100000 11110010 Current state Next state Input

13. – 12 – CSCE 211H Fall 2007 4d. Finish design of A (using D flip-flop) D(A,B,C,X) = CX AB 00 01 11 10 00 01 11 10 X 0011 0101 0101 0101 A B C AB’ AC’X’ A’BC A’BX

14. – 13 – CSCE 211H Fall 2007 4d. Finish design of A (using JK flip-flop) JA(A,B,C,X) = CX AB 00 01 11 10 00 01 11 10 X 00XX 01XX 01XX 01XX A B C BX BC

15. – 14 – CSCE 211H Fall 2007 4d. Finish design of A (using JK flip-flop) KA(A,B,C,X) = CX AB 00 01 11 10 00 01 11 10 X XX00 XX10 XX10 XX10 A B C BX BC

16. – 15 – CSCE 211H Fall 2007   (4 pts) Give VHDL for a 4x1 mux. entity is port( S1, S0: in bit; D3, D2, D1, D0: in bit; entity mux is port( S1, S0: in bit; D3, D2, D1, D0: in bit; Y: out bit); Y: out bit); end mux; Architecture M_arch of mux is begin Y <= D0 and not S1 and not S0 or D1 and not S1 and S0 or D2 and S1 and not S0 or D3 and S1 and S0; end M_arch;

17. – 16 – CSCE 211H Fall 2007 5. VHDL   (2 pts) What keyword would appear in a structural specification and immediately distinguish it from a behavioral specification? Portmap (…)   (4 pts) Assuming a 5 bit Carry look ahead unit, what is the VHDL for Gblock? Architecture of CLU is CLUarch begin Gblock <= G4 or G3 and P4 or G2 and P3 and P4 or G1 and P2 and P3 and P4 or G0 and P1 and P2 and P3 and P4; end of CLUarch;

18. – 17 – CSCE 211H Fall 2007 6a.Draw the logic diagram for an increment register.

19. – 18 – CSCE 211H Fall 2007 6b.Draw the logic diagram for an decrement register.

20. – 19 – CSCE 211H Fall 2007 6c. Combine

21. – 20 – CSCE 211H Fall 2007 7a. Draw a 1x4 demultiplexer x

22. – 21 – CSCE 211H Fall 2007 4-bit CLU Figure from Lecture 8 slide??? Partial Full Adder from Mano Gi = Xi and Yi Pi = Xi xor Yi = Xi and not Yi or not Xi and Yi Si = (Xi and not Yi and not C) or (not Xi and Yi and not C) or (not Xi and not Yi and C) or (Xi and Yi and C) This requires 7 “and” gates, and so is not implementable.

23. – 22 – CSCE 211H Fall 2007 PLA for PFA: Gi, Pi and …from Xi, Yi, C Xi Yi Gi = Xi and Yi Pi = Xi xor Yi = Xi and not Yi or not Xi and Yi Gi Pi

24. – 23 – CSCE 211H Fall 2007 PLA for PFA: Sumi from Xi, Yi, Ci Xi Yi Si = (Xi and not Yi and not C) or (not Xi and Yi and not C) or (not Xi and not Yi and C) or (Xi and Yi and C) Sumi Ci