1. Pro Asic3 - Radiation test at CHARM Christophe Godichal – BE/BI/QP christophe.godichal@cern.ch 1

2. Test Setup         2

3.  40 GBTx Elinks  80 lines in the FPGA  2 use for Reset, Enable flag  78 use for the test logic 3

4. FPGA Configuration Test Logic used 52% of the FPGA 4

5. Test Logic  16 Shift-Register with different combinaison of logic gate between register  Without logic gate between registers  NOT gates  AND gates  OR gates  12 Shift-Register TMR with the same combinaison of the Shift-register without TMR 5

6. Test Logic: Shift-Register  Objective: SEU detection  Register arrangment  2 SR with 350 reg. placed « randomly » by the compiler  3 SR with 350 reg. placed manually at the extreme of the FPGA 32 bit shift register (manual placement) Long connection in the fabric 6

7. Shift-Register with Logic Gates  Shift-Registers with 8 NOT gates between each register  Objective  SEU detection  SET detection @40MHz  2 SR with 350 reg. placed « randomly » by the compiler  3 SR with 350 reg. placed manually at the extreme of the FPGA  Shift-Registers with 8 AND gates between each register  Sensibility of SEU and SET  3 SR with 350 reg. placed manually at the extreme of the FPGA  Shift-Registers with 8 Or gate between each register  Sensibility of SEU and SET  3 SR with 350 reg. placed manually at the extreme of the FPGA 7

8. Shift-Register With « TMR »  Shift-Registers with « TMR »  SEU Immune, SET in the voter  3 Simple SR, 3 with 8 NOT gate, 3 with 8 AND gate, 3 with 8 OR gate (all SR with 350 reg TMR)  Test is used to compare sensibility of Shift-Register with TMR and without TMR 8

9. Results - TID results Type of SR Manual Placement in the FPGA Placed by the CompilerShift-Register TMR Gy SR_0485479489 SR_1499467478 SR_2538 486 SR_NOT_0513492475 SR_NOT_1501490461 SR_NOT_2502 494 SR_AND_0504 481 SR_AND_1499 477 SR_AND_2514 474 SR_OR_0515 511 SR_OR_1 459 SR_OR_2 485  Manual placement in the FPGA has failed from 485Gy to 538 Gy  Placed by the compiler has failed from 467Gy to 492Gy  Shift-Register TMR has failed from 461Gy to 511Gy  FPGA Stopped working at 752Gy 9

10. Results #errors and Cross-Section Type Total Nb of Register Total Nb of Errors Cross- Section Cross Section uncertainty Simple17502679.14E-14 5.59E-15 Not Gate17502568.76E-14 5.47E-15 And Gate10501468.33E-14 6.89E-15 Or Gate10501568.90E-14 7.12E-15  Without TMR 10

11. Results #errors and Cross-Section  With TMR Type Total Nb of Register Mean (λ) std dev (σ) Cross- Section Cross Section uncertainty Simple1050 123.466.84E-151.98E-15 Not Gate 1050 93.005.13E-151.71E-15 And Gate 1050 52.242.85E-151.28E-15 Or Gate 1050 103.165.70E-151.80E-15 11

12.  The I/O of the Shift-Register with TMR are not TMR too  We have 2 register in the input and 1 register in the output port   What is the probability to have one error on these i/o port ? Results Confidence on TMR results Type#I/O reg Cross- Section Error I/O reg probability Simple39.14E-140.46 Not Gate38.76E-140.44 And Gate38.33E-140.42 Or Gate38.90E-140.45 12

13. Results Difference between SR not TMR and SR TMR Type No TMRTMR Improvement σσ Simple9.14E-146.84E-1513.35 Not Gate8.76E-145.13E-1517.07 And Gate8.33E-142.85E-1529.20 Or Gate8.90E-145.70E-1515.60 13

14. Conclusion  All shift register stopped around 500Gy  The ProAsic dies around 750Gy  We have few errors on TMR-ed chain, so the statistics or not really good  We can suppose error in the I/O cell in the Shift-Register TMR  Future testing can be programmed to test more in details the propagation delays 14