1. CMOS Dynamic Power Consumption When CMOS logic is toggled, a current pulse will occur at transition and charge transfer between the voltage rails will take place through the capacitance load.

2. Figure 11.5-1. (a) CMOS inverter and (b) transfer curve

3. The following nomenclature should be helpful to the CMOS interpretation and analysis V TN = threshold voltage for nMOS transistor V TP = threshold voltage for pMOS transistor V GN = gate voltage for nMOS transistor V GP = gate voltage for pMOS transistor V GSN = gate-source voltage for nMOS transistor = V GN – GND V GSP = gate-source voltage for pMOS transistor = V GP – V + M N = nMOS transistor M P = pMOS transistor V OH (output high) = V+ V OL (output low) = GND V DN = drain voltage for nMOS transistor V DP = drain voltage for pMOS transistor K N = conduction coefficient for nMOS transistor K P = conduction coefficient for pMOS transistor

4. As shown by the transfer curve and by equation (11.4-2b) the nMOS transistor M N will be in saturation (a.k.a. active mode) when V DN > V GN – V TN with current I N = K N (V GSN – V TN ) 2 (11.5-1a) Since V GN = V I and V DN = V O this boundary is shown by the dashed line V I – V O = = V TN. Likewise the pMOS transistor will be in saturation (= active) mode when V O < V I – V TP with boundary given by the dashed line V GD (P) = V I – V O = V TP.. The current drawn by M P in saturation is I P = K P (V GSP – V TP ) 2 (11.5-1b) where V GSP = V GP – V+

5. Both M N and M P are in saturation when V O is between the two (dashed) boundary lines, for which I N = K N (V GSN – V TN ) 2 = I P = K P (V GSP – V TP ) 2 Since V GN = V GP = V I then K N (V I – V TN ) 2 = K P (V I – V + – V TP ) 2 (11.5-2b) The solution to (11.5-2b) is V I = V IT is defined as the inverter threshold and corresponds to the value of V I for the vertical segment of the V O vs V I transfer curve. Using the negative root to resolve V I, V I = V IT

6. It is more effective to use K R = K N /K P = conduction strength of the pull-down transistor relative to that of the pull-up transistor, for which the transition input V IT is then (11.5-3b) No current transpires when the inverter is at V OH or V OL. But current will occur when the circuit is in transition, since both transistors will then be conducting. At transition a current pulse will result with peak maximum I MAX = K N (V IT – V TN ) 2 (11.5-4) The strength ratio K R is called the aspect ratio. The inverter threshold (V IT ) = input at which V O is toggled from HI to LO (or from LO to HI).

7. Over the range V TN < V I < (V + + V TP ) an approximately triangular impulse of current will occur, as represented by figure 11.51(b). Its span  V is also a measure of interest  V in =  V = (V + + V TP ) – V TN = V + – |V TP | – |V TN | (11.5-5) The power consumed during a single transition is (11.5-6) Where the factor ½ is a reflection of the triangular distribution represented by figure 11.5-2.

8. Figure 11.5-2. I(V) during transition, CMOS inverter Each transition takes a quick but finite amount of time  t. Transition will occur twice for each cycle. Assuming that V I is linear with respect to t then this action may be resolved as a time average, i.e

9. where T = period of the transition, = 1/f. Consequently the power consumed by current pulse is P TRAN = f × [  t × I MAX  V] (11.5-8) The current pulses are not the major villain behind CMOS dynamic power consumption. The principal power consumption is due to the step transfer of charge between the voltage rails through the load capacitance C L, i.e. = f × C L V + 2 (11.5-9)

10. Equations (11.5-8) and (11.5-9) show that the power budget for CMOS logic is almost entirely dynamic power (defined by frequency). Since slow plodding circuits are an anathema, we may prefer to run at relatively high frequencies (GHz) and pay the penalty in power dissipation. Consequently this speed power option is also represented by a dynamic current measure for which (11.5-10a) with measure in  A/MHz or nA/MHz (11.5-10b)

11. EXAMPLE 11.5-1: A 3.0-volt CMOS technology for which K N = K P = 50  A/V 2 and V TN = -V TP = 0.5V is driving a load C L = 10fF (next stage input capacitance) and operating at average frequency f = 500MHz. The transition time between upper and lower rails  t = 0.2ns Determine: (a) V IT and I MAX, (b) P TRAN and P Q, and (c) I TRAN and I Q. (a) Aspect ratio K R = 1.0 and V TN = -V TP SOLUTION: → V IT = ½ V + (≡ balanced inverter.) = 1.5V I MAX = K N (V IT – V TN ) 2 = 50 × (1.5 – 0.5) 2 = 50  A Since  V = 3.0 – (0.5+0.5) = 2.0V Then P TRAN = f × [  t × I MAX  V] = 0.5GHz × (0.2ns × 50  A × 2.0V= 10  W

12. by equation (11.5-9), P Q will be P Q = = f × C L V + 2 = 0.5GHz × 10fF × 3.0 2 = 45  W By equations (11.5-9a) and (11.5-9b) we have dynamic currents = 6.67nA/MHz = 30nA/MHz For why power levels are important, consider the density of CMOS circuits and apply the power levels represented by example 11.5-1 to the following example (Example 11.5-2).

13. EXAMPLE 11.5-2: A synaptic-enhancement wig makes use of a 0.25  m, 2.0 V CMOS logic technology for which t OX = 8.6nm. The technology is used in a logic circuit for which the nMOS and pMOS transistors have W N = 1.2  m and W P = 3.0  m, respectively. Gate length L = 0.25  m. The logic gates are toggled (on the average) at a frequency of 200MHz. Determine: (a) Load capacitance C L for each logic gate (assuming C L = another like gate). (c) If each logic gate has 10 transistors (5 nMOS and 5 pMOS) with gate footprint 7  m x 5  m, how many logic gates (what size FPGA) can be mounted on the cross-section of a human hair (50  m diameter) (b) Dynamic power P Q used by one gate (in  W). (d) How much dynamic current in nA/MHz is required for each hair? (e) For a wig of 50,000 hairs what is the maximum speed (freq) at which it can be toggled if the power consumption (and heat) is to be kept under 5W?

14. SOLUTION: C L is the input capacitance for the next stage, for which C L = Cgate(nMOS) + Cgate(pMOS) Where C OX =(.0345fF/  m)/.0086  m = 4.0 fF/  m 2 so that (a) C L = 4.0 × [(1.2 +3.0) × 0.25] = 4.2 fF andP Q = f × C L V + 2 = 0.2GHz × 4.2fF × 2.0 2 = 3.36  W The geometrical considerations for a hair cross-section are represented by figure E11.5-2 and shows that the number of gates of footprint size (w × l ) that fit within the hair cross-section of diameter = D are

15.  43 gates (c)So the power required for 1 hair Figure E11.5-2. Hair cross-section: Die centers must lie within the elliptical area in order to avoid edge clipping = 144  W = 43 × 3.36  W (d) The dynamic current is = 360nA/MHz

16. (e) for the biophysical constraint P(max) = 5.0W P MAX = N × f × (I Q × V) And N = 50,000 =.05M Then 5.0 =.05M × (0.36  A/MHz) × 2.0 × f → f = 100/0.72 ≅ 138 MHZ Although this is not the clocking speed it still should be an indication of diminished expectations.

17. Other contributions to the CMOS power budget are associated with the ‘fault’ zone defined by V TN < V I < (V + - |V TP |). For any V in that happens to pause within this zone, conduction between the voltage rails will occur and the resultant I × V will add to the power budget. Since input logic levels are not just defined by the transistors but also by the capacitances and the charge sharing that takes place during logic transactions, an input voltage may be left in the fault zone. The consequence is illustrated by figure 11.5-4.

18. Figure 11.5-4. The cursor shows the effect of a logic outcome at V gate = 1.91V for a V OH = 3.0V technology. Current I = 2.03  A results and adds an extra power drain of 3.0V × 2.03  A = 6.09  W

19. The fault represented by figure 11.5-4 is a consequence of the refresh and execute cycle of CMOS architectures for which charge residing on a transmission line may be insufficient to pull up the logic input to V OH (min). This action is represented by figure 11.5-5 for which the V 2 = V gate outcome is due to charge redistribution. Figure 11.5-5. Charge redistribution (a.k.a. charge splitting) Charge redistribution yields a voltage on the gate of

20. EXAMPLE 11.5-3: A 3.0V technology has an interconnect capacitance C N = 30fF charged to 2.88V by a phased logic cycle. It is used to charge up a logic gate with total gate capacitance C G = Cgate(nMOS) + Cgate(pMOS) = 15fF SOLUTION: = 1.92V which will probably not cause a logic fault but will add to the power budget.

21. The rest of the story and collateral to logic level faults is that V IT should lie as close to the midpoint between power rails as possible. This requires that the pull- up and pull-down be balanced, which is the same as requiring that the conduction coefficients K N = K P. This requires a second look at the listings of the technology parameters. Consider the T67R technology shown by figure 11.5-6 ** and notice that the UO (mobility) is considerably weaker for pMOS devices than it is for nMOS devices.

22. Figure 11.5-6. Example BSIM3V4 technology tables (0.25 micron TSMC T67R)

23. For K N = K P The fabrication step for gate oxidation is concurrent to both nMOS and pMOS devices, so t OX and C OX are the same for both. And since the lengths are usually elected to be the same (i.e. L N = L P = L(min)) then the pMOS width is given by (11.5-11) (balanced inverter)

24. EXAMPLE 11.5-4: A 2.0V CMOS gate array is constructed using the 0.25mm TSMC T67R technology with MOS transistors of minimum feature size L = L(min) = 0.25  m and nMOSFETs with W N = 0.8  m. Determine: (a) pMOS transistor width needed for balanced V IT. (b) Input capacitance C G (a) From figure 11.5-6 the mobilities for nMOS and pMOS, respectively, are: UO = 311.7 and UO = 105.4 so the pMOS transistors should be of width SOLUTION: = 2.4  m

25. (b) from (a) and the fact that t OX = 5.5nm and C OX = e OX / t OX =.0345/.0055 = 6.3 fF/mm 2 Then C G = Cgate(nMOS) + Cgate(pMOS) = C OX × (W N + W P )L = 6.3 × (0.8 + 3.2) × 0.25 = 6.3 fF

26. PORTFOLIO and SUMMARY(c) CMOS: dynamic power consumption

27. Questions?