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02/12/20101F. Anghinolfi ABCN 130 nm Discussion Overview of the list of activities toward a first version of ABCN in 130nm Slides for specific domains.

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Presentation on theme: "02/12/20101F. Anghinolfi ABCN 130 nm Discussion Overview of the list of activities toward a first version of ABCN in 130nm Slides for specific domains."— Presentation transcript:

1 02/12/20101F. Anghinolfi ABCN 130 nm Discussion Overview of the list of activities toward a first version of ABCN in 130nm Slides for specific domains (in black) : Front-End RAM design Data and Command format DCDC implementation The way to progress (milestones etc…)

2 02/12/20102F. Anghinolfi ABCN 130 nm Discussion End 2010Mid 2011 End 2011 Obtain Protos FE design DC/DC and SP SEU Logic Obtain RAM block Sub miss ion Protos results ABCN full verilog code Mid 2012 RAM SEU test FE specs Data format specs TESTS DESIGN

3 02/12/20103F. Anghinolfi ABCN 130 nm Design Tasks ElementWork 1Institute/personTime periodCondition FE redesignRedesignJanQ2 2011 According to specs FE Bias/DAC & layout Bias/DAC & layoutJan + ?Q3 2011 RAM blocksRAM generatorCERN/MEQ3 2011 RAM blockstest Q3 2011SEU test RAM controlVerilog codeFrancisQ3 2011 Command DecoderVerilog codeFrancisQ3 2011 Data Compression LogicVerilog codeDaniel/GenevaQ3 2011 Readout LogicVerilog code Q4 2011 Verilog code Q1 2012+ 3 months min

4 02/12/20104F. Anghinolfi ABCN 130 nm Design Tasks ElementWork 1Institute/personTime periodCondition I/O parameters Spice simulation + bidirectional designMitch/PENN Readout data formatSpecification Strips readout groupEnd March 2011 Include L0/L1 preview Y Freeze at Oxford AUW CD data formatSpecification Strips readout groupEnd March 2011 Include L0/L1 preview Y Freeze at Oxford AUW All digitalP&RKrakow/CERN 1st semester 2012Krzysztof + ? Final chip layout assemblyKrakow/CERN 1st semester 2012Krzysztof + ?

5 02/12/20105F. Anghinolfi ABCN 130 nm : Module Controller Chip ElementWork 1Institute/personTime periodCondition MCCVerilog model To check with the ABCN data format definition MCC Specification/ DesignPENN Compatibility to GBT

6 02/12/20106F. Anghinolfi ABCN 130 nm : Gain 100mV/fC Linear range 4fC (saturation at 6fC) Peaking time 22ns Current consumption of the front end channel; Iinput+80uA (Iinput = 100-160uA) Power consumption (1.2V supply); 220 – 290uW / channel 130nm Front-end (J. Kaplon)

7 02/12/20107F. Anghinolfi ABCN 130 nm : Channel 22um x 700um Chip width; – channels; 256 x 22um = 5.6mm – bias + decoupling; 500um – Pads; 600um – DACs + bandgap; 500um? – Total; 7.2mm  two questions to module: Is it OK? How much we can increase (if necessary) this number? 130nm Front-end (J. Kaplon)

8 02/12/20108F. Anghinolfi ABCN 130 nm : 130nm Front-end (Barrel layout proposal, UK, Geneva, KEK) Max width 7.5 mm Would like only FE on top edge Data, clock, command on sides – Maximizing spacing between pairs, no redunancy Ground, power and chip ID on bottom 7.5 mm FE bonds only (4 rows of 64) Token and Data (2 pairs) BCO, L1, Com, Clk, Reset (5 pairs) Ground, Power, Chip ID

9 02/12/20109F. Anghinolfi ABCN 130 nm : 130nm Front-end (Barrel layout proposal, UK, Geneva, KEK) Would like FE bond pads to take full width of ASIC – Ground pads if needed below FE connections Ground pads would have to bond to the side, use same pad shape as for BE Would like ~50x200  m pads with 100  m spacing between rows 200  m 100  m Ground (if needed) 1100  m

10 02/12/201010F. Anghinolfi ABCN 130 nm : RAM RAM cell (2.2x2.5um 2 ) and RAM generator design work is currently started in PH/ME (C. Paillard + student, not specific to ATLAS) Best case availability : Summer 2011, 256x256 block 1 st version does not include ECC (ECC may be needed for long latency time as in L0/L1 architecture) Support from experiments welcome for TID/SEU radiation tests (Summer 2011) Availability best case : Summer 2011 We will build regular contacts with PH/ME to understand specifications and progress, tests to be carried on

11 02/12/201011F. Anghinolfi ABCN 130 nm : Digital Functions (Missing) one person for building the code for the new readout part (Missing) one person for building the code for the L0/L1 inclusion Specifications of readout and commands formats should be completed soon  should include L0/L1 format requirements Aim is to have a complete chip verilog description Q1 2012 Covers HDL description for RAM control, DCL, Readout Data format specifications should be frozen at end of March 2011 (AUW)

12 02/12/201012F. Anghinolfi ABCN 130 nm : Digital Functions HeaderData N Fixed size data packet 1 chip HeaderDataHeaderData Next chip No need of Data concat. Btw. chips No Constraint btw.chips Multiply nbe of headers Occupies BW

13 02/12/201013F. Anghinolfi ABCN 130 nm : Digital Functions L0 1 L0 2 R3 1 R3 2 L1 1 L1 2 L0ID 1 L0ID 2 Fixed Latency No fixed Latency Time IDGeographical ID 0.4-1MHz rate 40-100KHz rate Ty pe L0IDEvent ERC L0 or L1 or Control Data or DCS Data Trigger command with L0/L1 capability Data content with L0/L1 capability

14 02/12/201014F. Anghinolfi ABCN 130 nm : Digital Functions Additional time estimated for L0/L1 : + 3 months at best (depending on complexity and availability of RAM generator) L0ID Mem Pipeline L1 buffer (Addressable Memory) DCLSER RR ROL BC WARAWARA PE @L0: RA=WA- Nlat WAcalcRAcalc @BC : WA=WA+1 R3 latency (3us ?)L1 latency and Event Buffer L0 Match L0ID W L0ID gen R L1 R3 L0 Mem WR L0

15 02/12/201015F. Anghinolfi ABCN 130 nm : Module Controller The verilog code of the MC (FPGA, ASIC) should be build at the same time as the readout code is written for ABCN130 to verify data transmission compatibility Also the compatibility with the GBT E-link has to be defined and verified (clock in & clock out frequencies, etc …)

16 Decisions Procedure 02/12/201016F. Anghinolfi Specifications for Front-End (detector segmentation & hybrid experts) : Target AUW 2011. Specification for CD and Data Format : Strips Architecture working group. Target AUW 2011.

17 Milestones 02/12/201017F. Anghinolfi End 2010Mid 2011 End 2011 Obtain Protos FE design DC/DC and SP SEU Logic Obtain RAM block Submi ssion Protos results ABCN full verilog code Mid 2012 RAM SEU test FE specs Data format specs TESTS DESIGN

18 Resources Issue 02/12/201018F. Anghinolfi Missing resources : One digital designer for the readout part of ABCN 130 One digital designer for the L0/L1 implementation One part time effort for MCC specifications fixing

19 Backup Slides 02/12/201019F. Anghinolfi

20 02/12/201020F. Anghinolfi ABCN 130 nm : Where we are V DD = 1.9 V V OUT = 926 mV I OUT = 60 mA C X = 1000 nF C L = 200 nF f = 1 MHz M1 (PFET) 28.2mm / 0.24μm M2 (NFET) 18.0mm / 0.30μm M3 (NFET) 18.0mm / 0.30μm M4 (NFET) 6.0mm / 0.30μm M1 Buffer M2 Buffer M3 Buffer M4 Buffer Clock Gen Power Efficiency = 97% (including all circuitry) Step-up converter design M. Bochenek

21 02/12/2010 21F. Anghinolfi ABCN 130 nm : Where we are 21 M1 (NFET) 980μm / 0.24μm M2 (NFET) 980μm / 0.24μm M4 (PFET) 2000μm / 0.24μm M3 (PFET) 2000μm / 0.24μm Clock Generator Level Shifter Level Shifter Buffer 2 Buffer 1 V DD = 0.9 V C PUMP = 470 nF V OUT = 1.55 V C LOAD = 470 nF I OUT = 32 mA f = 500 kHz Total area = 0.04 mm 2 (200 x 190 μm 2 ) Power Efficiency = 85% (including all circuitry) Step-up converter design M. Bochenek

22 02/12/201022F. Anghinolfi ABCN 130 nm : Where we are (status) SEU Logic test Slow Command decoder Fast Command decoder Serial Register xx-SEU (4 bits, static) yy-SEU (7 bits, static) Serial Out yy- REGSEU (7 bits, one clk) RTL exists SEU Logic part (F. Anghinolfi, K. Swientek) SPP Elements (M. Newcomer, N. Dressnandt)

23 Techno: stick to 130nm 256 channels, one sided Analogue : test of the front-end to be done as soon as it is back (December) L0: could be skipped for first 130nm version Radiation hardness: should be implemented Memory: need to find a good memory block. The one from IBM is not rad hard. Mitch to discuss with a US company. Effort started at CERN PH/ME. Switched capacitor DC-DC: it should be possible to use the block (prototype block expected in December for tests) Serial power : elements (shunt transistor) should be implemented Readout data format: fixed length to be implemented as it is the simplest and that with the new luminosity target it's very likely to be good enough 02/12/201023F. Anghinolfi ABCN 130 nm Discussion

24 ABCN-130 : number of channels FE pads 4 rows 1mm x 10.0mm 256 FE channels Width : 0.7mm Height : 10.0mm (7.2 mm min) 22um pitch Max digital area 2mm x 10.0mm 10.0mm (7.2mm min) 4.0mm 256 ABCN 25 Size (same scale) 02/12/201024F. Anghinolfi 7.7mm 7.5mm

25 WE SHOULD ALLOW OPERATION WITH DIGITAL VOLTAGE RANGE FROM 1.5V TO 0.9V (for Lite, incl. on hybrids) Lite ABCN-130 Powering 02/12/201025F. Anghinolfi This is justified by : The SEU cross section is strongly depending on the VDD of registers The standard cells characterisations are valid from … to … (not know now) Power consumption optimization vs. other parameters (frequency, voltage margin, digital noise, total dose) WE SHOULD EVALUATE HOW THIS CONSTRAINT IS AFFECTING THE SERIAL OR DC/DC POWER DISTRIBUTION developments during the prototype phase

26 256 channel ABCN-130 Powering (Low VDDD) 02/12/201026F. Anghinolfi DC/DC DC-DC DC/DC LDO Serial Power 1 2.4V 1.8V Shunt Serial Power 2 ShuntDC/DC 1.2V 0.9V 1.2V Analogue (45mA) 0.9V Digital (102mA) Analogue (45mA) Digital (102mA) 1.2V Analogue (45mA)

27 256 channel ABCN-130 Powering (Std VDDD) 02/12/201027F. Anghinolfi DC/DC DC-DC DC/DC 2.4V Serial Power Shunt 1.2V 1.2V Analogue (45mA) 1.2V Digital (102mA) 1.2V Analogue (45mA) Even in the case of “one source” for analogue and digital, remains the issue of using LDO for analogue power quality

28 ABCN-130 Data Transmission Basically 2 mechanisms were under discussion : Data packets built with data from adjacent chips (data concatenation constraints as for ABCD) Independent Data packets (per chip, each packet contains its full identifiers) (impact on BW, compatibility with track trigger data, …) 02/12/201028F. Anghinolfi Assumption : due to reduced BW requirement (to be proven) the last schema becomes preferable

29 Data packets built with data from adjacent chips : – With Token (as ABCN now) : timing constraint, workable in 130nm – Xon/Xoff : no token timing constraint, one FIFO and some add. Logic in each chip ABCN-130 Data Transmission FEI tk data FEI WE data There are 2 variants, one does not requires WE at each chip (see backup slide) 02/12/201029F. Anghinolfi

30 We may use a simple Xon/Xoff mechanism in case of independent data packets (not dependancy on exact chip to chip timing) The track trigger readout priority is also in favor of the “short” independent data packets method ABCN-130 Data Transmission 02/12/201030F. Anghinolfi

31 In ABCN-25 the redundancy has resulted in : – Adoption of a Bidirectional data flow from chip-to chip (affects only the I/O circuits, very little impact on logic) that I believe we should maintain (free to transmit data either side of a chip to its neighbour or MC) – Dual clock and COM inputs The main impact is for hybrid design (carry dual clock and COM lines along hybrid) ABCN-130 REDUNDANCY 02/12/201031F. Anghinolfi

32 Schedule Full description of the (Lite) chip(s) mid of 2011 Floorplan and layout for submission in period in period Q1-Q2 2012 Schedule subject to commitments, should be assessed soon, (also in conjunction with the MC design ?) 02/12/201032F. Anghinolfi

33 Schedule 02/12/201033F. Anghinolfi May 2010Mid 2011 Mid 2012 Now FE design DC/DC and Regulators SEU structures I/Os, DCS ? Partial HDL code (ABCN, MC ?) Submission (ABCN, MC ?) Test results RAM block

34 Cost estimate and resources 02/12/201034F. Anghinolfi The projected MPW submission cost is around 30KUSD (3KUSD/mm2) One Engineering run in 130nm is 405KUSD (2 wafers) + 3.6KUSD/wafer Cost Resources (manpower) We should assess them (organisation/institutes) : Seeking young people List tasks and distribute Select appropriate software tools Organize a dedicated seminar ? (Organization of design team, incl. MCC?)

35 ABCN 130nm Open Issues 02/12/201035F. Anghinolfi 1. Define precisely design resources for 2 next years Organize a dedicated seminar ? (Specifications, organization of design team, list of tasks) 2. On design elements : Clarify implementation of blocks for powering CRITICAL  RAM block development (1 year time frame) Agreement on readout schema Simultaneous development of MCC (with interface to GBT) ? Rad & SEU tolerance

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