1. EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

2. Staffs Dr. Muhammad Imran Ahmad m.imran@unimap.edu.my Rafikha Aliana A.Raof rafikha@unimap.edu.my Dr. Phaklen Ehkan phaklen@unimap.edu.my

3. Textbook

4.  Chap. 1: Introduction to Comp. Architecture  Chap. 2: Foundation to Comp. Architecture  Chap. 3: Design Methodology  Chap. 4: Central Processing Unit (CPU) Basics  Chap. 5: Processor Internals  Chap. 6: Enhancing CPU Performance  Chap. 7: CPU Externals  Chap. 8: Practical Embedded CPUs  Chap. 9: Evolution of Computer Architecture ------- refer teaching plan--------- Contents (lecture)

5.  VHDL as hardware programming  Altera Quartus II as a development platform  Altera DE FPGA board Laboratory

6. VHDL – Design Flow VHDL entry Netlist (Gate level) Optimised Netlist (Gate level) Physical device compilation optimization simulation synthesis simulation Place & route

7. Code Structure – Fundamental VHDL units Library declaration Entity Architecture Basic VHDL Code

8. Example VHDL code for FA unit library ieee; use ieee.std_logic_1164.all; entity full_adder is port (a,b,cin : in bit; s, cout : out bit; end full_adder; architecture dataflow of full_adder is begin s <= a XOR b XOR cin; cout <= (a AND b) OR (a AND cin) OR (b AND cin); END dataflow; circuit

9.  Lecture: Monday: 03-04pm (CommE) – DK5 Friday: 08-10 (CommE) – BPU7  Laboratory (MKM7): G1: 11 – 01pm G2: 10 – 12pm Contact Hours

10. Test, Quiz & Assignment = 30% Lab. Component = 20% Final Exam = 50% Assessment

11. End of Intro..