1. Sequential Equivalence Checking for Clock-Gated Circuits Hamid Savoj Robert Brayton Niklas Een Alan Mishchenko Department of EECS University of California, Berkeley

2. 2 Overview Motivation Motivation Notation Notation Theorems Theorems Asymmetry Asymmetry Implementation Implementation Experiments Experiments Conclusions Conclusions

3. 3 Clock Gating Two circuits, A and B, should be verified equivalent when an enabling signal E has been used for clock gating in B

4. 4 Motivation Useful sequential circuit transformations include Useful sequential circuit transformations include Clock gating, loop removal, redundancy removal Clock gating, loop removal, redundancy removal However, sequential equivalence checking (SEC) remains a hard computational problem However, sequential equivalence checking (SEC) remains a hard computational problem A better SEC methodology is required A better SEC methodology is required We develop a SEC methodology, which We develop a SEC methodology, which Works for some useful sequential transforms Works for some useful sequential transforms Reduces SEC to CEC, which has lower complexity Reduces SEC to CEC, which has lower complexity SEC is PSPACE-complete; CEC is NP-hard SEC is PSPACE-complete; CEC is NP-hard

5. 5 Notation A is a sequential circuit A is a sequential circuit A n denotes the combinational circuit derived as shown below where A n denotes the combinational circuit derived as shown below where A is unrolled n times A is unrolled n times outputs of A n are the n POs from each frame plus the FF inputs at the end of the n th frame outputs of A n are the n POs from each frame plus the FF inputs at the end of the n th frame inputs are n PIs plus initial FF outputs inputs are n PIs plus initial FF outputs AAAA FF Outputs FF Inputs PO PI

6. 6 Notation A and B are two sequential circuits with A and B are two sequential circuits with the same inputs and the same inputs and the same number of FFs the same number of FFs [ A n,B k ] is the combinational circuit connected through their FFs inputs/outputs [ A n,B k ] is the combinational circuit connected through their FFs inputs/outputs AAAA BBB [ A 4,B 3 ] FF inputs FF outputs PI PO FF outputs

7. 7 Notation If C and D are combinational circuits, C = D denotes that they are combinationally equivalent If C and D are combinational circuits, C = D denotes that they are combinationally equivalent If A and B are sequential circuits, denotes that A and B are sequentially equivalent If A and B are sequential circuits, denotes that A and B are sequentially equivalent

8. 8 Observability Theorem Theorem 1: If there exists a 1-1 mapping between the FFs of A and B, such that Theorem 1: If there exists a 1-1 mapping between the FFs of A and B, such that, then for any initial state. i.e. A and B are sequentially equivalent i.e. A and B are sequentially equivalent

9. 9 Reducing SEC to CEC PI 1 PI 2 PI 3 If all outputs are, then Why do we need a 1-1 mapping?

10. 10 Proof of Theorem 1 Statement: - POs of Frame 1 are equal - POs of Frame 2 are equal - Flops of Frame 2 are equal Proof: (see picture)

11. 11 Controlability Theorem Theorem 2: If there exists a 1-1 mapping between the FFs of A and B, such that Theorem 2: If there exists a 1-1 mapping between the FFs of A and B, such that, then, then for any initial state that can be reached by A after n cycles. for any initial state that can be reached by A after n cycles.

12. 12 Controlability/Observability Theorem Theorem 3: on the subset of states that can be reached by A after one cycle. Theorem 3: on the subset of states that can be reached by A after one cycle.

13. 13 How about combined observability/controllability? AAA ABA == = A-controllable, A-observable? (justify – propagate) AAA ABB == = Theorem 2 (A-controllability) AAB ABB == = Theorem 3 (A-controllable, B-observable) AAA BAA == = Theorem 1 (A-observability) =

14. 14 Counter-example AAA ABA == =

15. 15 0 1 Q RS DQ e RS DQ a 0 1 Verification Asymmetry: AA = BA b 0 1 RS DQ e RS DQ a 0 1 b F1F1 F2F2 F1F1 F2F2 e(0) a(0) 0 1 b(0) F 1  0 1 c v F 2  c(0) F 2  F 1  Q(1) Q 0 1 c(1) F 1  Q(2) e(1) F 2  a(1) 0 1 b(1) F 2  e(0) a(0) 0 1 F 1  0 1 F 2  c(0) F 2  F 1  Q(1) 0 1 c(1) F 1  Q(2) e(1) F 2  a(1) 0 1 b(1) F 2  F 2  A B AA BA

16. 16 0 1 Q RS DQ e RS DQ a 0 1 b 0 1 RS DQ e RS DQ a 0 1 b F1F1 F2F2 F1F1 F2F2 e(0) a(0) 0 1 b(0) F 1  0 1 c v F 2  c(0) F 2  F 1  Q(1) Q 0 1 c(1) F 1  Q(2) e(1) F 2  a(1) 0 1 F 2  e(0) a(0) 0 1 F 1  0 1 F 2  c(0) F 2  F 1  Q(1) 0 1 c(1) F 1  Q(2) e(1) F 2  a(1) 0 1 F 2  F 2  A B AB BB Verification Asymmetry: AB != BB

17. 17 Improvements in CEC Resulting CEC problems have deep logic and are hard Resulting CEC problems have deep logic and are hard Typically CEC is solved by SAT sweeping (detecting and proving internal candidate equivalences); in this case, there are many candidates and many of them are hard to prove Typically CEC is solved by SAT sweeping (detecting and proving internal candidate equivalences); in this case, there are many candidates and many of them are hard to prove Developed a general CEC procedure, which skips some intermediate equivalences Developed a general CEC procedure, which skips some intermediate equivalences The result for the relevant CEC problems was The result for the relevant CEC problems was 5x reduction in runtime 5x reduction in runtime solved previously unsolved problems solved previously unsolved problems D2D1 Given a combinational miter with equivalence class {A, B, A’, B’} - try to prove A=A’ and B=B’ - do not try to prove A = B, A = B’, etc B A A’ B’

18. 18 Implementation The proposed algorithm is implemented as command absec in ABC The proposed algorithm is implemented as command absec in ABC The command takes two networks and the number of timeframes to unfold The command takes two networks and the number of timeframes to unfold

19. 19 Experimental Results Six industrial benchmarks were transformed using sequential clock-gating transforms, based on intuitively correct sequential ODC arguments Six industrial benchmarks were transformed using sequential clock-gating transforms, based on intuitively correct sequential ODC arguments

20. 20 Experimental Results K is the number of timeframes K is the number of timeframes New is proposed implementation (absec) New is proposed implementation (absec) General is general SEC (dsec) General is general SEC (dsec) Runtime is in minutes on Intel(R) Xeon(R) CPU X5570 @ 2.93GHz Runtime is in minutes on Intel(R) Xeon(R) CPU X5570 @ 2.93GHz

21. 21 Conclusions We introduced several scenarios when SEC can be replaced by CEC with considerable reduction of computational effort The methods are conservative; if the checks fail, nothing is implied about non-equivalence Some conditions when the checks are expected to succeed, include sequential clock-gating and redundancy removal Future work focuses on sequential synthesis that is provably verifiable using the proposed method

22. 22 Abstract Often sequential logic synthesis can lead to substantially easier verification problems, compared to the general- case for sequential equivalence checking (SEC). This talk discusses conditions when SEC can be reduced to combinational equivalence checking (CEC). These can be applied to many sequential clock gating transforms, where correctness is argued intuitively using a finite unrolling of a sequential design. A method based on these theorems was applied to six large industrial examples. It completed on all examples and was about 30x faster on the three examples where the conventional engine was able to finish. Often sequential logic synthesis can lead to substantially easier verification problems, compared to the general- case for sequential equivalence checking (SEC). This talk discusses conditions when SEC can be reduced to combinational equivalence checking (CEC). These can be applied to many sequential clock gating transforms, where correctness is argued intuitively using a finite unrolling of a sequential design. A method based on these theorems was applied to six large industrial examples. It completed on all examples and was about 30x faster on the three examples where the conventional engine was able to finish.