1. 1-D Array of Perforated Diode Neutron Detectors Walter McNeil, Steven Bellinger, Troy Unruh, Chris Henderson, Phil Ugorowski, Bryce Morris-Lee, Russell Taylor *, Douglas McGregor Semiconductor Materials and Radiological Technologies (SMART) Laboratory Dept. of Mechanical and Nuclear Engineering Kansas State University, Manhattan, KS 66506 * EDL, Electronic Design Laboratory Kansas State University Manhattan, KS 66506

2.  Project Goals  Perforated Diode Detector Structure  Array Design  System Performance  Conclusions  Future Work OBJECTIVE Outline

3. SANS Detector Array –10 cm x 4 cm Array –100 micron Pitch –Trench Perforations 30 microns by > 100 microns Deep –> 10% Efficiency 10 cm 4 cm PROJECT GOALS

4. Detector Design

5. Perforated Diode Neutron Detectors Neutron Counting Efficiency –Thin-film limited to 4.5% –Perforated Device up to 35% 6 LiF is most convenient –Triton: 2.73 MeV –Alpha: 2.05 MeV DETECTOR STRUCTURE

6. Perforated Diode Neutron Detectors Compact geometry High counting efficiency Low voltage operation –0-5 (V) reverse bias Very adaptable design Large quantity fabrication DETECTOR STRUCTURE

7. 1-D Array Chip 30 µm wide trenches 20 µm wide diffused diode 5 µm spacing between trench and diode Powder fill with 6 LiF 6 LiF Evaporated Film Humiseal ® protective layer ARRAY DESIGN

8. 1-D Array System Chip bonds to daughter board –Connection to connector –Some passive components Connects to motherboard –PATARA amplifiers –Comparators One threshold for each PATARA chip –Digital out to computer CAT6 cable ARRAY DESIGN

9. Human Interface ARRAY DESIGN

10. Performance

11. Signal Processing PATARA ASIC 32-Channel amplifier chip –0.5 Volt pulse height –1 µsec pulse width ARRAY PERFORMANCE

12. Spatial Resolution ARRAY PERFORMANCE Gd Neutron Beam Flux CTS POSITION

13. Spatial Resolution Error-function fit Derivative to get Gaussian ARRAY PERFORMANCE

14. 300 μm Slit Experiment HFIR at ORNL –HB-2D Future Development beam line –32-channel collection –300 µm slit resolved ARRAY PERFORMANCE

15. Quality Testing Dead Pixels? Process Yield? 16 Mounted chips is too late! ARRAY PERFORMANCE

16. CONCLUSIONS Successfully integrated system –10 6 count-rates should be possible Excellent spatial resolution –119 µm, FWHM Efficiency exceeds thin-film detectors –3x, with room for improvement Can test chips before assembly Ready to assemble 1024 pixel array Conclusions

17. Future Work

18. FUTURE WORK Stacking Arrays 60 µm

19. FUTURE WORK 40 µm

20.  Defense Threat Reduction Agency, contract DTRA-01-03- C-0051  National Science Foundation, IMR-MIP Grant, 2004- present  K-State Electronic Design Laboratory  Chuck Britton and University of Tennessee, Knoxville ACKNOWLEDGMENTS