1. Based on slides from D. Patterson and www-inst.eecs.berkeley.edu/~cs152/ COM 249 – Computer Organization and Assembly Language Chapter 3 Arithmetic For Computers

2. Arithmetic Where we've been: –Performance (seconds, cycles, instructions) –Abstractions: Instruction Set Architecture Assembly Language and Machine Language What's up ahead: –Implementing the Architecture 32 operation result a b ALU

3. Bits are just bits (no inherent meaning) — conventions define relationship between bits and numbers Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2 n -1 Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number) How do we represent negative numbers? i.e., which bit patterns will represent which numbers? What is the largest number that can be represented in a computer? How does hardware REALLY multiply or divide numbers? Numbers

4. Sign Magnitude: One's Complement Two's Complement 000 = +0000 = +0000 = +0 001 = +1001 = +1001 = +1 010 = +2010 = +2010 = +2 011 = +3011 = +3011 = +3 100 = -0100 = -3100 = -4 101 = -1101 = -2101 = -3 110 = -2110 = -1110 = -2 111 = -3111 = -0111 = -1 Issues: balance, number of zeros, ease of operations Which one is best? Why? Possible Representations

5. 32 bit signed numbers: 0000 0000 0000 0000 0000 0000 0000 0000 two = 0 ten 0000 0000 0000 0000 0000 0000 0000 0001 two = + 1 ten 0000 0000 0000 0000 0000 0000 0000 0010 two = + 2 ten... 0111 1111 1111 1111 1111 1111 1111 1110 two = + 2,147,483,646 ten 0111 1111 1111 1111 1111 1111 1111 1111 two = + 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0000 two = – 2,147,483,648 ten 1000 0000 0000 0000 0000 0000 0000 0001 two = – 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0010 two = – 2,147,483,646 ten... 1111 1111 1111 1111 1111 1111 1111 1101 two = – 3 ten 1111 1111 1111 1111 1111 1111 1111 1110 two = – 2 ten 1111 1111 1111 1111 1111 1111 1111 1111 two = – 1 ten maxint minint MIPS

6. Negating a two's complement number: invert all bits and add 1 –remember: “negate” and “invert” are quite different! –Example: 8 bit representation of 5 –Binary 0000 0101 ( 5 two ) –Invert 1111 1010 –Add 1+ 1 1111 1011 ( -5 two ) Interpreting a two’s complement number First bit is sign bit 1 x 2 -7 + 1 x2 6 + 1x 2 5 + 1x2 4 + 1x 2 3 + 0x 2 2 + 1x2 1 + 1x 2 0 -128 + 64 + 32 + 16 + 8+ 0+ 2 + 1 = -5 Adding a number and it’s twos complement equals zero! Two's Complement Operations

7. Let’s try it Simple Simulator http://scholar.hw.ac.uk/site/computing/activ ity12.asp?outline=http://scholar.hw.ac.uk/site/computing/activ ity12.asp?outline http://scholar.hw.ac.uk/site/computing/topic18.asp?outline= http://scholar.hw.ac.uk/site/computing/topic18.asp?outline

8. Two's Complement Operations Converting n bit numbers into numbers with more than n bits: –MIPS 16 bit immediate gets converted to 32 bits for arithmetic –copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 –Function of signed load is to copy sign into register ( sign extension) (identical for 32 bit word into 32 bit register) –purpose is to place correct representation of number in register –"sign extension” (lbu vs. lb) MIPS -(load byte unsigned) lbu - works with unsigned integers - (load byte) lb treats byte as signed and extends sign

9. Just like in grade school (carry / borrow 1s) 0111 0111 0110 + 0110- 0110- 0101 Two's complement operations easy –subtraction using addition of negative numbers 0111 + 1010 Overflow (result too large for finite computer word): –e.g., adding two n-bit numbers does not always yield an n-bit number 1111 + 0001 note that overflow term is somewhat misleading, 10000 it does not mean a carry “overflowed” http://chortle.ccsu.ctstateu.edu/AssemblyTutorial/Chapter- 08/ass08_1.html Addition & Subtraction

10. Overflow Overflow occurs when the result of an operation on n bits > n bits Example: adding two 8 bit values 1001 1101 157 +1111 1011 +251 11001 1000 408 overflow!

11. Overflow occurs when the result cannot be represented in the available hardware No overflow when adding a positive and a negative number No overflow when signs are the same for subtraction Overflow occurs when the value affects the sign: –overflow when adding two positives yields a negative –or, adding two negatives gives a positive –or, subtract a negative from a positive and get a negative –or, subtract a positive from a negative and get a positive Consider the operations A + B, and A – B ( See table p. 172) –Can overflow occur if B is 0 ? –Can overflow occur if A is 0 ? Detecting Overflow

12. An exception (interrupt) occurs –Control jumps to predefined address for exception –Interrupted address is saved for possible resumption –add, addi, sub cause exceptions on overflow but –addu, addiu, subu DO NOT cause exceptions Details based on software system / language –example: flight control vs. homework assignment Don't always want to detect overflow — new MIPS instructions: addu, addiu, subu note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons Effects of Overflow

13. Signed and Unsigned Memory addresses are always non-negative ( starting with zero…) Sometimes a 1 in the most significant digit represents a negative number which is less than any positive number, which begins with a 0 Unsigned numbers – 1 in the most significant digit represents a number larger than any that begins with a 0

14. Signed vs. Unsigned Comparison MIPS – two versions of set on less than comparison –for signed integers slt (set on less than) and slti (set on less than immediate) –for unsigned integers sltu(set on less than unsigned) and sltiu(set on less than immediate unsigned) Example: ( See example p. 165 also) slt $s1,$s2,$s3 means if ( $s2 < $s3) $s1 = 1 //compare two’s complement else $s1 =0 slti $s1,$s2, 100 means if ( $s2 < 100) $s1 = 1 //compare to constant else $s1 =0 sltu $s1,$s2,$s3 means if ( $s2 < $s3) $s1 = 1 //compares unsigned else $s1 =0 sltiu $s1,$s2, 100 means if ( $s2 < 100) $s1 = 1 //compare to constant else $s1 =0

15. Shortcuts To negate two’s complement binary number –Invert each bit and add one to result –Based on based on observation that the sum of a number and the representation of its inverse = -1 To convert a number with n bits to a number represented with more than n bits –Take the most significant bit (sign bit) from the shorter number, and replicate it to fill the new bits of the longer number. ( Copy the original bits into the right portion of the new word – called sign extension)

16. More Examples References for Two’s Complement notation http://www.duke.edu/~twf/cps104/twoscomp.html http://en.wikipedia.org/wiki/Two's_complement http://mathforum.org/library/drmath/sets/select/dm_twos_compleme nt.htmlhttp://mathforum.org/library/drmath/sets/select/dm_twos_compleme nt.html http://www.fact-index.com/t/tw/two_s_complement.html http://www.hal-pc.org/~clyndes/computer- arithmetic/twoscomplement.htmlhttp://www.hal-pc.org/~clyndes/computer- arithmetic/twoscomplement.html http://www.vb-helper.com/tutorial_twos_complement.html http://web.bvu.edu/faculty/traylor/CS_Help_Stuff/Two's%20Compl ement.htmhttp://web.bvu.edu/faculty/traylor/CS_Help_Stuff/Two's%20Compl ement.htm

17. More Examples Some conversion examples http://people.csail.mit.edu/u/h/hammond/publi c_html/teaching/cs1001/2Comp.htmlhttp://people.csail.mit.edu/u/h/hammond/publi c_html/teaching/cs1001/2Comp.html Internal representation http://www.cs.angelo.edu/~egarcia/lab22.html