1. 1 Arithmetic Building Blocks Today: Signed ArithmeticFirst Hour: Signed Arithmetic –Section 5.1 of Katz’s Textbook –In-class Activity #1 Second Hour: Adder Circuits. Section 5.1 of Katz’s Textbook –In-class Activity #2

2. 2 Recap: Building Blocks we’ve learned about thus far: –Programmable Logic Arrays –Multiplexors & De-multiplexors –Read-only Memory Today: Representation of Negative Numbers Building Blocks: Adders and Subtractors

3. 3 Sign & Magnitude Representation Sign equals the High order bit:Sign equals the High order bit:0 = positive or zero (non-negative) 1 = negative Magnitude equals the three low order bits:Magnitude equals the three low order bits: 0 = 000 thru 7 = 111 n The number range =  7 for 4 bit numbers; for n bits,  2 n-1 -1 Two Representations for 0 (redundant & problematic) 0000 0111 0011 1011 1111 1110 1101 1100 1010 1001 1000 0110 0101 0100 0010 0001 +0+0+0+0 +1+1 +2+2 +3+3 +4+4 +5+5 +6+6 +7+7 -0-0-0-0 -1 -2-2 -3-3 -4-4 -5-5 -6-6 -7-7 0 100 = + 4 1 100 = - 4 + sign - sign 4 bit example

4. 4 Sign & Magnitude 4 + 3 7 0100 0011 0111 -4 + (-3) -7 1100 1011 1111 Sign of the result: the same as the operands' sign (Don’t add sign bits) Operands have the same sign 4 + (-3) 1 0100 1011 0001 -4 + 3 1100 0011 1001 Sign of the result: the sign of operand with the larger magnitude Magnitude of the result: subtraction operation Operands have different signs Addition

5. 5 Sign & Magnitude 4 - 3 1 0100 0011 0001 -4 - (-3) 1100 1011 1001 Sign of the result: the same as the operands' sign (Don’t subtract sign bits) Operands have the same sign 4 - (-3) 7 0100 1011 0111 -4 - 3 -7 1100 0011 1111 Sign of the result: the sign of operand with the larger magnitude Magnitude of the result: addition operation Operands have different signs Subtraction

6. 6 AdditionAddition –Addition when signs of operand the same –Subtraction when signs of operands differ –Must compare magnitudes to determine sign of result SubtractionSubtraction –Subtraction when signs of operand the same –Addition when signs of operands differ –Must compare magnitudes to determine sign of result Complicated implementationComplicated implementation –Adder unit –Subtractor unit –Comparator unit Sign & Magnitude

7. 7 Sign Magnitude One's Complement Two's Complement 000 = +0000 = +0000 = +0 001 = +1001 = +1001 = +1 010 = +2010 = +2010 = +2 011 = +3011 = +3011 = +3 100 = - 0100 = - 3100 = - 4 101 = - 1101 = - 2101 = - 3 110 = - 2110 = - 1110 = - 2 111 = - 3111 = - 0111 = - 1 Issues: balance, number of zeros, ease of operations Two’s complement is ideal because hardware is simpler Same circuit for addition and subtraction Signed Representations

8. 8 Pizza Pie Diagram Only one zero

9. 9 MSB = The Sign Bit MSB=0 For zero and positive numbers Positive numbers are the same as in Sign-Magnitude

10. 10 MSB = The Sign Bit MSB=1 For negative numbers

11. 11 More Negative Numbers than Positives One more negative number. No +4

12. 12 Recognizing Overflow 3+1 = -4 Wrong sign Indicates overflow

13. 13 Carries 0 1 1 1 1 0 0 0 0 0 1 1 5 3 -8 0 1 0 1 0 0 1 1 1 0 0 0 -7 -2 7 1 0 0 1 1 1 1 0 0 1 1 1 527527 0 1 0 1 0 0 1 0 0 1 1 1 -3 -5 -8 1 1 0 1 1 0 1 1 1 0 0 0 Twos-Complement Calculations overflow no overflow Overflow occurs when the carry in to the sign position does not equal the carry out of the sign position Also, wrong sign  Overflow

14. 14 AdditionAddition –Addition not dependent on the signs of operand –No need to compare magnitudes to determine sign of result SubtractionSubtraction –Subtraction is treated as an addition –Add the negative of the subtrahend to the minuend Simple implementationSimple implementation –Adder unit –Negation circuit unit Twos-Complement Simpler addition/subtraction scheme makes twos-complement the most common choice for integer number systems within digital systems Simpler addition/subtraction scheme makes twos-complement the most common choice for integer number systems within digital systems

15. 15 Do Activity #1 Now Get to know two’s complement arithmetic

16. 16 Half Adder Adder With twos-complement, adders are sufficient Half-adder Carry Sum A i B i A i B i Sum 0 0 0 0 1 1 1 0 1 1 1 0 Carry 0 1

17. 17 Full Adder S = A  B  CI CO = B CI + A CI + A B = (A + B) CI + A B S = A  B  CI CO = B CI + A CI + A B = (A + B) CI + A B A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CI 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 CO 0 0 0 1 0 1 1 1 A B CI 0 1 00011110 01 00 0 1 A B CI 0 1 00011110 0 0 0 1 0 1 1 1 S CO 1 1

18. 18 Multi-Bit Adder A3B3 S3 A2B2 S2 A1B1 S1 A0B0 S0C1C2C3 C0 using Full Adder Units FA C4

19. 19 Full Adder Full Adder from Half Adders S = A  B  CI Alternative Implementation: 5 Gates - 2 XOR, 2 AND, & 1 OR CO = A B + (A  B) CI = A B + B CI + A CI + Half Adder A B Half Adder A  B CI SS CO (A  B) CI A B S CO Standard Approach: 6 Gates A A A B B B CI S CO

20. 20 AB CO S +CI AB CO S +CI AB CO S +CI AB CO S +CI 01 Add/Subtract A 3 B 3 B 3 01 A 2 B 2 B 2 01 A 1 B 1 B 1 01 A 0 B 0 B 0 Sel S 3 S 2 S 1 S 0 Adder/Subtractor A - B = A + (-B) = A + (B + 1) 2s complement negative Overflow

21. 21 How Fast is it? A i B i Inputs A i & B i are available immediately, @ time 0 C I The C I from lower bit additions take time. Suppose CI is available @ time N one gate delay from N to compute S one gate delay from N to compute S A B CI S @0 @N @1 @N+ 1 two gate delays from N to compute CO two gate delays from N to compute CO A A B B CI CO @0 @N @1 @N+ 1 @N+ 2

22. 22 The Carry bit Ripples Slowly Notation: @n means signal is available after n gate delays 4 stage adder A 0 B 0 C 0 S 0 @2 A 1 B 1 C 1 @3 S 1 @4 A 2 B 2 C 2 @5 S 2 @6 A 3 B 3 C 3 @7 S 3 @8 C 4 @9 0 1 2 3 Critical delay: Critical delay: the propagation of carry from low to high order stages

23. 23 Timing Diagram The propagation of carry from low to high order stages 1111 + 0001 worst case addition 1111 + 0001 worst case addition T0: Inputs to the adder are valid T2: Stage 0 carry out (C1) T4: Stage 1 carry out (C2) T6: Stage 2 carry out (C3) T8: Stage 3 carry out (C4) N + 2 delays to compute sum But last carry is not ready until 6 delays later, N = 6 until 6 delays later, N = 6 N + 2 delays to compute sum But last carry is not ready until 6 delays later, N = 6 until 6 delays later, N = 6 T0T2T4T6T8 S0, C1 ValidS1, C2 ValidS2, C3 ValidS3, C4 Valid

24. 24 A Faster Adder To make our adder faster, we must compute the carry faster Just how fast can it be? Ultimately, the adder is just a large combinational circuit. We should be able to realize it using 2-state logic. Price to pay: more gates. Plan: Express each carry directly in terms of the A i, B i, and C 0

25. 25 Observe: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 CI 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 CO 0 0 0 1 0 1 1 1 CO = 0 CO = CI CO = 1 (if AB=1, Carry out =1 regardless of carry in) CARRY GENERATED if A  B, Carry out =Carry in CARRY PROPAGATED

26. 26 Carry Lookahead Logic Carry Generate G i = A i B i Carry Generate G i = A i B i must generate carry when A = B = 1 Carry Propagate P i = A i  B i Carry Propagate P i = A i  B i carry in will equal carry out here Carry Generate G i = A i B i Carry Generate G i = A i B i must generate carry when A = B = 1 Carry Propagate P i = A i  B i Carry Propagate P i = A i  B i carry in will equal carry out here S i = A i  B i  C i = P i  C i C i+1 = A i B i + A i C i + B i C i = A i B i + C i (A i + B i ) = A i B i + C i (A i + B i ) = A i B i + C i (A i  B i ) = A i B i + C i (A i  B i ) = G i + C i P i = G i + C i P i Let CI = C i, then CO = C i+1 show logical equivalence

27. 27 Expand it out C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 two-level Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage 0!

28. 28 Implementation Increasingly complex logic Adder with Sum, Propagate and Generate Outputs Adder with Sum, Propagate and Generate Outputs P i @ 1 gate delay CiCi S i @ 2 gate delays BiBi AiAi G i @ 1 gate delay

29. 29 Carry Lookahead Delays First Level Carry Lookahead Carry lookahead logic generates individual carries @3 Result: sums computed faster Result: sums computed faster A 0 B 0 C 0 S 0 @2 A 1 B 1 C 1 @3 S 1 @4 A 2 B 2 C 2 @3 S 2 @4 A 3 B 3 C 3 @3 S 3 @4 C 4 @3 Reduced slowest output from 8 to 4 gate delays!

30. 30 Building Larger Adders Second Level Carry Look-ahead 4 bit adders with internal carry look-ahead Second level carry lookahead unit, extends look-ahead to 16 bits 4 bit adders with internal carry look-ahead Second level carry lookahead unit, extends look-ahead to 16 bits

31. 31 Do Activity #2 Now Due: End of Class Today RETAIN THE LAST PAGE (#3)!! For Next Class: Bring Randy Katz Textbook, & TTL Data Book Required Reading: – Sec 3.4 & 5.3 of Katz This reading is necessary for getting points in the Studio Activity!