1. Digital Logic & Design Dr. Waseem Ikram Lecture No. 25

2. J-K flip-flop with Asynchronous Preset and Clear inputs

3. Logic Symbol of a J-K flip-flop with Asynchronous inputs

4. InputOutput Q t+1 00Invalid 011 100 11Clocked operation PRE CLR Truth table of J-K flip-flop with Asynchronous inputs

5. Timing diagram of a J-K flip-flop with Preset and Clear inputs

6. Master-Slave flip-flop

7. InputOutpu t CLKJKQ t+1 Pulse00QtQt 010 101 11 Truth table of the Master-Slave J- K flip-flop t Q

8. Timing diagram of a Master Slave J-K flip- flop

9. Propagation Delay, clock to low-to-high transition of the output

10. Propagation Delay, clock to high- to-low transition of the output

11. Propagation Delay, preset to low- to-high transition of the output

12. Set-up time for a D flip-flop

13. Propagation Delay, clear to high-to-low transition of the output

14. Hold time for a D flip-flop

15. Circuit diagram of a One-Shot

16. Timing diagram of a One-Shot

17. Timing diagram of a non retriggerable One-Shot Trigger Output of One-Shot t 1 t 2 t 3 t 4 t 5 t 6

18. Timing diagram of a non- retriggerable One-Shot with ignored triggers Trigger Output of One-Shot t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10

19. Recap D flip-flop applications Data Storage Synchronizing Asynchronous Inputs Parallel data Transfer J-K flip-flop J-K flip-flop applications Sequence Detector Frequency Divider Shift Register Counter

20. Asynchronous Inputs J-K flip-flop with asynch. inputs (fig 1a) Logic symbol asynch. J-K flip-flop (fig 1b) Function table (tab1) Timing diagram (fig 1c)

21. Master-Slave flip-flop Master Slave flip-flop (fig 2a) Function table (tab 2) Timing diagram (fig 2b)

22. Operating Conditions Flip-Flop Operating Conditions Propagation delay (fig 3,4,5,6) Set-up time (fig 7) Hold Time (fig 8) Max clock frequency Pulse Width Power Dissipation

23. Multivibrators Mono-Stable Multi-vibrator (fig 9) Non-Retriggerable (fig 10) Retriggerable (fig 11)