1. A new family of pixel detectors for high frame rate X- ray applications Roberto Dinapoli †, Anna Bergamaschi, Beat Henrich, Roland Horisberger, Ian Johnson, Philipp Kraft, Aldo Mozzanica, Bernd Schmitt, Xintian Shi, Dominic Suter † Corresponding author: roberto.dinapoli@psi.ch The charge signal from the sensor is amplified and filtered by the low noise preamplifier and following shaper with tunable shaping time. The shaped signal is fed to a comparator with a reference voltage that is given by a global threshold and the on-pixel trim DAC (6 bit). An incoming signal exceeding this threshold will toggle the comparator state. If the chip is in “expose” mode (Enable high) and the pixel didn't overflow, the comparator pulse increments the digital counter by one. At the end of the exposure time the counter content is stored temporarily in a pixel buffer, and the counter is reset to allow immediately a new exposure. During At the Swiss Light Source (SLS) we are developing a new family of hybrid, single photon counting detectors for high frame rate X-ray applications. Systems up to 9 Mpixel will be built, targeting mainly protein crystallography, small angle scattering and coherent diffraction imaging. The readout chip was received from fabrication the third week of May and is at present being integrated in the test setup. The chip is designed with Hardening By Design techniques (HBD: enclosed layout transistors, p-guard rings) to obtain high radiation tolerance from a standard commercial CMOS technology. Readout chip main features Readout speed To reduce to a very minimum the dead time between frames the chip features double buffered storage, so a next frame can already be taken while the previous one is being readout. The estimated dead time between frames (needed to perform the *Limited by counter depth ** Limited by analog frontend speed buffering and counters reset) is about 1 μs. Moreover, the maximum frame rate can be adjusted using the selectable length of the pixel counter, ranging from 4 bits (lower flux-very high frame rate applications) to 12 bits. In 4 bit mode the frame rate can be up to about 24 Kframes/s. To reduce the data throughput in applications with longer exposure times, several images can be summed on the readout control board. This also increases the actual “virtual” pixel counter depth up to 32 bits. Mode of operation Max. frame rate (100MHz DDR clock) Maximum counting rate 4 bits24 kHz380kHz/pix* 8 bits12 kHz~1MHz/pix** 12 bits8 kHz~1MHz/pix** Pixel architecture the “Readout” phase the state of the pixel buffers is transferred to the chip periphery, where they are readout via a 100 MHz Double Data Rate (DDR), 32-line parallel bus. Moreover, every pixel can be addressed individually for testing and preliminary calibration prior to bump bonding to a sensor. The calibration circuitry of the selected pixel injects a known charge into the pixel input and tracks the shaper output of the chosen channel, so that it can be monitored with an oscilloscope. Precise calibration is usually performed after bump bonding to a sensor with a monochromatic x-ray source. Introduction Module and readout system architecture One detector module consists of an array of 8 readout chips bump-bonded to a big pixel silicon sensor of about ~78 x 39 mm 2. A module will then have ~0.5 Mpixel. Several modules can be tiled to form big area detectors; systems ranging from a single module up to 18 modules (9 Mpixel, ~550 cm 2 ) are planned. Every module will be served by two readout boards which will perform data readout and formatting plus data storage on a local memory (~33 kFrames in 4bit mode). The readout boards can transmit the data to a control PC via a standard 1 Gb ETHERNET connection. The system is designed to be upgradable to 10 Gb ETHERNET, to be able to sustain the full data flow at maximum frame rate from module to PC with no local storage. This will remove the bottleneck, and allow for continuous data taking at the highest frame rate. Chip readout scheme The readout architecture is targeting very fast frame rates. For this reason a high level of parallelism is embedded in the chip. A full row of pixel counter nibbles (4 x 256 bits) is transferred to the periphery readout logic in parallel. Here, the bits of 8 columns are grouped to form a “supercolumn”, serialised and presented at the output with a faster clock (100MHz DDR). The readout of the resulting 32 supercolumns happens in parallel on 32 readout lines. To increase chip testability a serial slow readout mode of operation is also implemented. Charge Sensitive (CS) Ampli-shaper output curves for different values of the shaping time control voltage Vrf. Vrf=-0.44 (high speed) Vrf=-0.34 (standard) Vrf=-0.14 (low noise) Vrf=-0.24 Paul Scherrer Institut, 5232 Villigen PSI, CH. The new readout chip keeps the noise and speed performance of the previous chip of the Pilatus family (Pilatus II) and improves it in every other respect; in particular pixel size (reduced >5x), pixel count (>11x), double buffering, but most of all readout speed (>1000x for big detectors). Technological process UMC 0.25 µm Power supplies1.1 V (analog), 2 V (digital), 1.8 V (I/O) Radiation toleranceRadiation tolerant design (>4 Mrad) Pixel array256 x 256 = 65536 Chip size19.3 x 20 mm 2 Other featuresOverflow control, XY-addressability and analog out for testing The readout chip Pixel size 75 x 75 µm 2 Gain 44.6 μV/e- Peaking time 31 ns Ret. to zero @ 1% 151 ns Noise (simulated) 135 e-rms Static power dissipation 8.8 μW/pixel Transistor count 430/pixel Pixel counter configurable (4,8,12 bit mode), binary, double buffered for continuous readout Threshold adjust 6 bit DAC/pixel The pixel* New sensor PII sensor Picture of a “single”, a pixel silicon sensor prototype which will be bonded to a single chip, close to a Pilatus II (PII) sensor. The smaller pixel size and bump bonding pitch are evident in the microscopy picture in the inset. ~2 cm *Simulations done with “standard” settings. “Low noise” or “high speed” settings can improve performance for applications with specific needs.